Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 268250 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 637667 1 T2 8 T3 2142 T11 2



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 524009 1 T2 5 T3 1703 T11 2
values[0x0] 168484 1 T2 5 T3 654 T4 3
values[0x1] 213424 1 T2 3 T3 1954 T4 3



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 184737 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 721180 1 T2 9 T3 3306 T11 2



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3553 1 T3 21 T5 40 T37 2
valid_sources[0x01] 3462 1 T3 11 T5 31 T43 33
valid_sources[0x02] 3026 1 T3 25 T5 24 T43 24
valid_sources[0x03] 3407 1 T3 19 T5 15 T43 22
valid_sources[0x04] 3256 1 T3 24 T5 39 T43 27
valid_sources[0x05] 3169 1 T3 14 T5 20 T43 28
valid_sources[0x06] 3752 1 T3 22 T5 46 T43 20
valid_sources[0x07] 3545 1 T2 1 T3 14 T5 40
valid_sources[0x08] 3384 1 T3 8 T5 29 T43 22
valid_sources[0x09] 3363 1 T3 14 T11 1 T5 25
valid_sources[0x0a] 3114 1 T3 19 T5 39 T43 20
valid_sources[0x0b] 3366 1 T3 20 T5 27 T43 24
valid_sources[0x0c] 3662 1 T3 11 T5 35 T43 19
valid_sources[0x0d] 3334 1 T3 31 T5 29 T43 21
valid_sources[0x0e] 3228 1 T3 14 T5 33 T43 25
valid_sources[0x0f] 3065 1 T3 15 T5 30 T43 24
valid_sources[0x10] 3302 1 T3 16 T5 39 T43 25
valid_sources[0x11] 3091 1 T3 20 T5 29 T43 19
valid_sources[0x12] 3549 1 T3 16 T5 22 T43 21
valid_sources[0x13] 3241 1 T3 35 T5 24 T43 20
valid_sources[0x14] 3632 1 T3 7 T5 22 T37 2
valid_sources[0x15] 3496 1 T3 21 T5 42 T43 29
valid_sources[0x16] 3505 1 T3 28 T5 22 T43 28
valid_sources[0x17] 3447 1 T3 35 T5 28 T43 26
valid_sources[0x18] 3543 1 T3 20 T5 33 T43 33
valid_sources[0x19] 3464 1 T3 23 T5 18 T32 1
valid_sources[0x1a] 2811 1 T3 7 T5 25 T43 37
valid_sources[0x1b] 3372 1 T3 14 T5 31 T43 40
valid_sources[0x1c] 3850 1 T3 15 T5 27 T43 28
valid_sources[0x1d] 3408 1 T3 14 T5 26 T43 20
valid_sources[0x1e] 3000 1 T3 6 T5 24 T43 17
valid_sources[0x1f] 3518 1 T3 18 T5 22 T43 28
valid_sources[0x20] 3222 1 T3 16 T5 34 T25 1
valid_sources[0x21] 3244 1 T3 11 T5 30 T43 24
valid_sources[0x22] 3585 1 T3 16 T5 25 T25 1
valid_sources[0x23] 3554 1 T3 13 T5 39 T43 21
valid_sources[0x24] 3806 1 T3 19 T5 30 T43 17
valid_sources[0x25] 4076 1 T2 1 T3 11 T5 35
valid_sources[0x26] 3607 1 T3 12 T5 48 T25 2
valid_sources[0x27] 3312 1 T2 1 T3 16 T5 30
valid_sources[0x28] 3548 1 T3 11 T5 47 T43 24
valid_sources[0x29] 3402 1 T3 22 T5 26 T43 21
valid_sources[0x2a] 3302 1 T3 15 T5 21 T43 24
valid_sources[0x2b] 3731 1 T3 29 T5 29 T43 31
valid_sources[0x2c] 3683 1 T3 14 T5 32 T43 23
valid_sources[0x2d] 3497 1 T2 1 T3 18 T5 30
valid_sources[0x2e] 3622 1 T3 19 T5 23 T43 25
valid_sources[0x2f] 3348 1 T3 20 T5 28 T43 26
valid_sources[0x30] 3544 1 T3 11 T5 37 T43 20
valid_sources[0x31] 14060 1 T3 17 T5 35 T43 23
valid_sources[0x32] 3554 1 T3 7 T5 36 T43 31
valid_sources[0x33] 3266 1 T3 13 T5 29 T43 28
valid_sources[0x34] 3233 1 T3 28 T5 27 T119 3
valid_sources[0x35] 3591 1 T3 29 T5 30 T43 26
valid_sources[0x36] 3422 1 T3 15 T5 30 T43 21
valid_sources[0x37] 4482 1 T2 1 T3 18 T5 20
valid_sources[0x38] 3172 1 T3 11 T5 32 T25 2
valid_sources[0x39] 3125 1 T3 19 T5 19 T43 34
valid_sources[0x3a] 3572 1 T3 18 T5 33 T43 27
valid_sources[0x3b] 3218 1 T3 15 T5 25 T43 20
valid_sources[0x3c] 3362 1 T3 7 T5 32 T43 21
valid_sources[0x3d] 3257 1 T2 1 T3 16 T5 32
valid_sources[0x3e] 3352 1 T3 17 T5 46 T43 36
valid_sources[0x3f] 4595 1 T3 18 T5 36 T43 26
valid_sources[0x40] 3474 1 T3 10 T4 1 T5 32
valid_sources[0x41] 3434 1 T3 7 T5 34 T9 10
valid_sources[0x42] 2992 1 T3 19 T5 40 T32 1
valid_sources[0x43] 3262 1 T3 13 T5 17 T43 23
valid_sources[0x44] 3378 1 T3 19 T5 36 T43 36
valid_sources[0x45] 3264 1 T3 3 T5 27 T43 26
valid_sources[0x46] 3216 1 T3 7 T5 33 T43 28
valid_sources[0x47] 3135 1 T3 21 T5 28 T43 27
valid_sources[0x48] 3486 1 T3 14 T5 45 T43 23
valid_sources[0x49] 3786 1 T3 29 T5 40 T43 28
valid_sources[0x4a] 3448 1 T2 1 T3 12 T5 42
valid_sources[0x4b] 3469 1 T3 20 T5 27 T43 28
valid_sources[0x4c] 3302 1 T3 11 T5 31 T43 22
valid_sources[0x4d] 3683 1 T3 18 T5 35 T43 39
valid_sources[0x4e] 3614 1 T3 14 T5 25 T113 1
valid_sources[0x4f] 3514 1 T3 16 T5 22 T43 34
valid_sources[0x50] 3193 1 T3 15 T5 34 T43 22
valid_sources[0x51] 3557 1 T3 11 T5 28 T43 34
valid_sources[0x52] 3431 1 T3 13 T5 28 T38 1
valid_sources[0x53] 3377 1 T3 22 T5 24 T43 22
valid_sources[0x54] 3264 1 T3 15 T5 27 T43 20
valid_sources[0x55] 3607 1 T3 14 T5 27 T43 23
valid_sources[0x56] 3358 1 T3 19 T5 39 T43 26
valid_sources[0x57] 3298 1 T3 13 T5 35 T43 28
valid_sources[0x58] 3669 1 T3 31 T5 30 T43 28
valid_sources[0x59] 3549 1 T3 13 T5 54 T43 22
valid_sources[0x5a] 3268 1 T3 17 T5 29 T43 26
valid_sources[0x5b] 3330 1 T3 12 T5 28 T43 24
valid_sources[0x5c] 3557 1 T3 22 T5 36 T38 20
valid_sources[0x5d] 3463 1 T3 15 T5 21 T43 32
valid_sources[0x5e] 3224 1 T3 11 T5 35 T37 1
valid_sources[0x5f] 4124 1 T3 21 T5 28 T43 28
valid_sources[0x60] 3420 1 T3 23 T5 41 T43 18
valid_sources[0x61] 3928 1 T3 7 T5 23 T38 20
valid_sources[0x62] 3340 1 T3 15 T5 30 T43 38
valid_sources[0x63] 3321 1 T3 8 T5 24 T43 33
valid_sources[0x64] 3300 1 T3 13 T5 48 T43 31
valid_sources[0x65] 3384 1 T3 20 T5 33 T43 25
valid_sources[0x66] 3389 1 T3 32 T5 35 T43 30
valid_sources[0x67] 4004 1 T3 19 T5 38 T43 26
valid_sources[0x68] 3193 1 T3 14 T5 25 T43 30
valid_sources[0x69] 3069 1 T3 17 T5 38 T37 1
valid_sources[0x6a] 3586 1 T3 12 T5 24 T32 1
valid_sources[0x6b] 3567 1 T3 13 T5 38 T43 20
valid_sources[0x6c] 3432 1 T3 22 T5 30 T59 1
valid_sources[0x6d] 3325 1 T2 1 T3 18 T5 19
valid_sources[0x6e] 5251 1 T3 11 T5 37 T25 1
valid_sources[0x6f] 3493 1 T3 16 T5 34 T43 19
valid_sources[0x70] 3696 1 T3 23 T5 21 T43 29
valid_sources[0x71] 3250 1 T3 18 T5 35 T43 28
valid_sources[0x72] 3893 1 T3 15 T5 42 T43 20
valid_sources[0x73] 3418 1 T3 18 T5 35 T43 25
valid_sources[0x74] 3251 1 T3 18 T5 20 T43 32
valid_sources[0x75] 3318 1 T3 23 T5 23 T37 1
valid_sources[0x76] 3375 1 T3 8 T5 39 T43 25
valid_sources[0x77] 3319 1 T3 16 T5 30 T37 2
valid_sources[0x78] 3310 1 T3 3 T5 33 T43 24
valid_sources[0x79] 3120 1 T3 21 T5 34 T43 39
valid_sources[0x7a] 3158 1 T3 19 T5 31 T43 25
valid_sources[0x7b] 3594 1 T3 9 T5 30 T43 21
valid_sources[0x7c] 4110 1 T3 19 T5 32 T43 30
valid_sources[0x7d] 3113 1 T3 10 T5 25 T43 22
valid_sources[0x7e] 3198 1 T3 12 T4 1 T5 27
valid_sources[0x7f] 4050 1 T3 16 T5 34 T43 25
valid_sources[0x80] 3075 1 T3 22 T5 38 T43 26



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 314159 1 T2 4 T3 1047 T11 2
values[0x0] all_enables biggest_size 162192 1 T2 2 T3 531 T4 3
values[0x1] all_enables biggest_size 161316 1 T2 2 T3 564 T5 1147


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 8768 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 96503 1 T1 1 T2 8 T3 2581



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 30870 1 T3 675 T5 1354 T43 1126
values[0x0] 36236 1 T1 1 T2 5 T3 994
values[0x1] 38165 1 T2 3 T3 1014 T33 9



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5911 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 99360 1 T1 1 T2 8 T3 2632



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 409 1 T3 5 T5 87 T43 17
valid_sources[0x01] 748 1 T3 17 T43 21 T103 9
valid_sources[0x02] 611 1 T3 7 T5 54 T43 21
valid_sources[0x03] 335 1 T3 6 T28 1 T43 23
valid_sources[0x04] 264 1 T3 11 T43 18 T103 7
valid_sources[0x05] 261 1 T3 12 T5 2 T43 17
valid_sources[0x06] 368 1 T3 12 T5 1 T43 28
valid_sources[0x07] 266 1 T3 9 T43 28 T103 6
valid_sources[0x08] 545 1 T3 16 T33 1 T25 1
valid_sources[0x09] 402 1 T3 16 T5 3 T43 15
valid_sources[0x0a] 491 1 T3 6 T43 23 T103 5
valid_sources[0x0b] 333 1 T3 5 T5 2 T43 16
valid_sources[0x0c] 266 1 T3 8 T43 17 T103 3
valid_sources[0x0d] 260 1 T3 14 T119 1 T43 16
valid_sources[0x0e] 577 1 T3 14 T5 78 T43 20
valid_sources[0x0f] 487 1 T3 11 T33 2 T43 17
valid_sources[0x10] 470 1 T3 12 T5 1 T43 15
valid_sources[0x11] 394 1 T3 4 T5 4 T43 18
valid_sources[0x12] 264 1 T3 16 T5 1 T43 19
valid_sources[0x13] 337 1 T3 8 T5 3 T43 19
valid_sources[0x14] 480 1 T3 8 T43 24 T103 8
valid_sources[0x15] 372 1 T3 7 T5 2 T43 16
valid_sources[0x16] 345 1 T3 12 T5 1 T43 17
valid_sources[0x17] 507 1 T3 10 T5 132 T43 21
valid_sources[0x18] 449 1 T3 11 T25 1 T43 29
valid_sources[0x19] 400 1 T3 12 T43 19 T103 4
valid_sources[0x1a] 380 1 T3 14 T5 1 T43 24
valid_sources[0x1b] 377 1 T3 12 T43 13 T103 6
valid_sources[0x1c] 336 1 T3 13 T43 23 T103 4
valid_sources[0x1d] 614 1 T3 10 T5 94 T43 21
valid_sources[0x1e] 493 1 T3 24 T5 2 T43 20
valid_sources[0x1f] 361 1 T3 9 T43 15 T103 2
valid_sources[0x20] 630 1 T3 13 T5 6 T43 16
valid_sources[0x21] 355 1 T3 8 T5 1 T37 2
valid_sources[0x22] 417 1 T3 9 T5 22 T130 1
valid_sources[0x23] 377 1 T3 4 T5 1 T43 21
valid_sources[0x24] 537 1 T3 7 T43 16 T112 1
valid_sources[0x25] 1377 1 T3 9 T43 19 T103 4
valid_sources[0x26] 300 1 T3 13 T43 15 T45 1
valid_sources[0x27] 351 1 T3 14 T43 23 T103 5
valid_sources[0x28] 334 1 T3 8 T34 1 T43 11
valid_sources[0x29] 261 1 T3 18 T25 1 T43 7
valid_sources[0x2a] 660 1 T3 7 T5 63 T37 1
valid_sources[0x2b] 526 1 T3 10 T43 24 T103 7
valid_sources[0x2c] 253 1 T3 9 T43 16 T103 4
valid_sources[0x2d] 326 1 T3 14 T5 2 T43 29
valid_sources[0x2e] 507 1 T3 12 T5 85 T110 1
valid_sources[0x2f] 395 1 T3 6 T43 12 T103 4
valid_sources[0x30] 338 1 T3 13 T5 2 T43 17
valid_sources[0x31] 261 1 T3 13 T5 3 T43 22
valid_sources[0x32] 407 1 T3 4 T43 17 T103 4
valid_sources[0x33] 296 1 T3 5 T43 15 T103 6
valid_sources[0x34] 277 1 T3 10 T5 1 T43 27
valid_sources[0x35] 370 1 T3 15 T5 96 T43 23
valid_sources[0x36] 310 1 T3 10 T5 53 T43 17
valid_sources[0x37] 550 1 T3 9 T12 1 T43 20
valid_sources[0x38] 332 1 T3 5 T43 20 T103 6
valid_sources[0x39] 295 1 T3 9 T5 1 T32 2
valid_sources[0x3a] 302 1 T3 10 T5 12 T43 24
valid_sources[0x3b] 410 1 T3 8 T43 16 T103 4
valid_sources[0x3c] 563 1 T3 11 T43 11 T200 2
valid_sources[0x3d] 312 1 T3 7 T5 4 T43 16
valid_sources[0x3e] 453 1 T3 9 T5 1 T43 24
valid_sources[0x3f] 291 1 T3 5 T114 1 T43 13
valid_sources[0x40] 699 1 T3 10 T5 141 T43 17
valid_sources[0x41] 283 1 T3 9 T43 17 T22 1
valid_sources[0x42] 305 1 T3 15 T43 24 T103 7
valid_sources[0x43] 427 1 T3 10 T33 1 T5 1
valid_sources[0x44] 669 1 T3 16 T5 130 T27 1
valid_sources[0x45] 309 1 T3 15 T201 1 T43 16
valid_sources[0x46] 916 1 T3 17 T5 1 T43 13
valid_sources[0x47] 226 1 T3 6 T5 1 T43 9
valid_sources[0x48] 530 1 T3 13 T43 16 T103 5
valid_sources[0x49] 379 1 T3 11 T43 21 T103 6
valid_sources[0x4a] 424 1 T3 13 T43 20 T103 5
valid_sources[0x4b] 520 1 T3 8 T5 1 T157 2
valid_sources[0x4c] 498 1 T3 15 T43 19 T103 3
valid_sources[0x4d] 396 1 T3 13 T43 23 T6 8
valid_sources[0x4e] 252 1 T3 11 T33 3 T43 19
valid_sources[0x4f] 336 1 T3 18 T43 18 T103 2
valid_sources[0x50] 244 1 T3 7 T4 5 T43 15
valid_sources[0x51] 417 1 T3 8 T5 57 T43 18
valid_sources[0x52] 271 1 T3 11 T5 3 T43 16
valid_sources[0x53] 423 1 T3 8 T5 3 T111 1
valid_sources[0x54] 278 1 T3 11 T5 2 T43 24
valid_sources[0x55] 653 1 T3 12 T43 17 T103 2
valid_sources[0x56] 327 1 T3 11 T43 7 T103 12
valid_sources[0x57] 382 1 T1 1 T3 6 T5 74
valid_sources[0x58] 373 1 T3 13 T4 1 T43 15
valid_sources[0x59] 365 1 T3 3 T4 1 T5 2
valid_sources[0x5a] 443 1 T3 5 T43 16 T42 1
valid_sources[0x5b] 575 1 T3 8 T5 167 T43 12
valid_sources[0x5c] 588 1 T3 15 T5 1 T43 18
valid_sources[0x5d] 353 1 T3 9 T5 81 T157 1
valid_sources[0x5e] 586 1 T3 15 T43 9 T103 4
valid_sources[0x5f] 447 1 T3 11 T33 1 T5 9
valid_sources[0x60] 347 1 T3 14 T48 1 T43 20
valid_sources[0x61] 465 1 T3 7 T5 112 T43 10
valid_sources[0x62] 326 1 T2 8 T3 12 T5 1
valid_sources[0x63] 277 1 T3 9 T5 27 T134 1
valid_sources[0x64] 450 1 T3 9 T5 131 T157 1
valid_sources[0x65] 332 1 T3 11 T5 1 T43 19
valid_sources[0x66] 413 1 T3 6 T111 1 T43 19
valid_sources[0x67] 328 1 T3 14 T43 17 T103 12
valid_sources[0x68] 511 1 T3 5 T5 1 T43 23
valid_sources[0x69] 520 1 T3 7 T43 17 T103 8
valid_sources[0x6a] 310 1 T3 9 T43 25 T103 3
valid_sources[0x6b] 325 1 T3 4 T157 3 T43 14
valid_sources[0x6c] 352 1 T3 3 T34 2 T5 51
valid_sources[0x6d] 576 1 T3 9 T29 1 T9 3
valid_sources[0x6e] 617 1 T3 15 T5 172 T113 1
valid_sources[0x6f] 258 1 T3 11 T43 15 T103 4
valid_sources[0x70] 431 1 T3 12 T43 21 T103 6
valid_sources[0x71] 289 1 T3 14 T43 14 T103 9
valid_sources[0x72] 244 1 T3 11 T5 1 T43 17
valid_sources[0x73] 530 1 T3 12 T43 18 T103 6
valid_sources[0x74] 273 1 T3 19 T34 1 T5 1
valid_sources[0x75] 687 1 T3 16 T5 27 T43 22
valid_sources[0x76] 489 1 T3 8 T5 1 T43 23
valid_sources[0x77] 624 1 T3 18 T5 1 T43 20
valid_sources[0x78] 332 1 T3 15 T43 17 T103 6
valid_sources[0x79] 365 1 T3 23 T43 22 T103 6
valid_sources[0x7a] 338 1 T3 8 T43 11 T103 7
valid_sources[0x7b] 293 1 T3 10 T157 2 T43 21
valid_sources[0x7c] 483 1 T3 6 T43 27 T103 4
valid_sources[0x7d] 276 1 T3 8 T33 1 T5 41
valid_sources[0x7e] 389 1 T3 17 T43 21 T103 5
valid_sources[0x7f] 628 1 T3 9 T5 165 T43 21
valid_sources[0x80] 443 1 T3 16 T43 19 T103 4



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 26174 1 T3 638 T5 1254 T43 1071
values[0x0] all_enables biggest_size 35169 1 T1 1 T2 5 T3 989
values[0x1] all_enables biggest_size 35160 1 T2 3 T3 954 T33 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%