SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1132963 | 1 | T2 | 13 | T3 | 10117 | T4 | 6 | ||||
auto[1] | 157022 | 1 | T3 | 4142 | T5 | 9213 | T38 | 80 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1289779 | 1 | T2 | 13 | T3 | 14259 | T4 | 6 | ||||
values[1] | 19 | 1 | T190 | 1 | T191 | 2 | T192 | 1 | ||||
values[2] | 6 | 1 | T171 | 3 | T191 | 1 | T193 | 1 | ||||
values[3] | 106 | 1 | T170 | 4 | T171 | 4 | T172 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1289761 | 1 | T2 | 13 | T3 | 14259 | T4 | 6 | ||||
values[1] | 20 | 1 | T170 | 1 | T171 | 1 | T172 | 2 | ||||
values[2] | 7 | 1 | T170 | 2 | T172 | 1 | T191 | 2 | ||||
values[3] | 102 | 1 | T170 | 2 | T171 | 11 | T172 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1289665 | 1 | T2 | 13 | T3 | 14259 | T4 | 6 | ||||
auto[TlIntgErrCmd] | 96 | 1 | T170 | 1 | T171 | 3 | T172 | 4 | ||||
auto[TlIntgErrData] | 114 | 1 | T170 | 4 | T171 | 10 | T172 | 13 | ||||
auto[TlIntgErrBoth] | 110 | 1 | T170 | 5 | T171 | 7 | T172 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 269237 | 0 | T1 | 1 | T2 | 8 | T3 | 6863 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 269026 | 1 | T1 | 1 | T2 | 8 | T3 | 6863 | ||||
values[1] | 24 | 1 | T170 | 1 | T171 | 1 | T172 | 1 | ||||
values[2] | 4 | 1 | T191 | 1 | T194 | 1 | T195 | 1 | ||||
values[3] | 114 | 1 | T170 | 2 | T171 | 6 | T172 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 269034 | 1 | T1 | 1 | T2 | 8 | T3 | 6863 | ||||
values[1] | 26 | 1 | T170 | 1 | T171 | 2 | T172 | 1 | ||||
values[2] | 6 | 1 | T171 | 1 | T172 | 1 | T190 | 1 | ||||
values[3] | 100 | 1 | T170 | 5 | T171 | 6 | T172 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 268917 | 1 | T1 | 1 | T2 | 8 | T3 | 6863 | ||||
auto[TlIntgErrCmd] | 117 | 1 | T170 | 2 | T171 | 4 | T172 | 7 | ||||
auto[TlIntgErrData] | 109 | 1 | T170 | 5 | T171 | 8 | T172 | 8 | ||||
auto[TlIntgErrBoth] | 94 | 1 | T170 | 3 | T171 | 8 | T172 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |