Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

638528

1

T2

5

T3

11784

T4

3

full_word

651457

1

T2

8

T3

2475

T4

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1289665	1			T2	13		T3	14259		T4	6
auto[TlIntgErrCmd]	96	1			T170	1		T171	3		T172	4
auto[TlIntgErrData]	114	1			T170	4		T171	10		T172	13
auto[TlIntgErrBoth]	110	1			T170	5		T171	7		T172	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

540559

1

T2

5

T3

2065

T5

3126

auto[1]

749426

1

T2

8

T3

12194

T4

6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	224605	1			T2	1		T3	975		T5	1596
auto[TlIntgErrNone]	partial	auto[1]	413631	1			T2	4		T3	10809		T4	3
auto[TlIntgErrNone]	full_word	auto[0]	315801	1			T2	4		T3	1090		T5	1530
auto[TlIntgErrNone]	full_word	auto[1]	335628	1			T2	4		T3	1385		T4	3
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T170	1		T172	1		T190	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T171	3		T172	3		T190	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T190	1		T196	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T194	1		T196	1		T197	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T170	2		T171	3		T172	7
auto[TlIntgErrData]	partial	auto[1]	42	1			T170	1		T171	6		T172	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T172	1		T198	1		T195	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T170	1		T171	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T170	3		T171	1		T172	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T170	2		T171	5		T172	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T171	1		T191	1		T199	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T190	1		T191	2		T193	1