Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108340809	122427	0	0
late_debug_enable_rd_A	108340809	10592	0	0
late_debug_enable_regwen_rd_A	108340809	9799	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108340809	122427	0	0
T3	90044	3170	0	0
T4	445465	0	0	0
T5	206779	8275	0	0
T11	14855	0	0	0
T12	162914	0	0	0
T27	40248	0	0	0
T29	314965	0	0	0
T32	385392	0	0	0
T33	3710	0	0	0
T34	2068	0	0	0
T43	0	5329	0	0
T56	0	11219	0	0
T82	0	1719	0	0
T101	0	10455	0	0
T102	0	6032	0	0
T103	0	1423	0	0
T116	0	3314	0	0
T117	0	2940	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108340809	10592	0	0
T82	0	907	0	0
T96	0	1419	0	0
T103	74876	534	0	0
T116	0	922	0	0
T117	0	1033	0	0
T121	0	49	0	0
T128	0	2	0	0
T152	0	78	0	0
T159	0	3	0	0
T160	0	266	0	0
T161	13076	0	0	0
T162	21015	0	0	0
T163	1340	0	0	0
T164	4105	0	0	0
T165	578283	0	0	0
T166	53640	0	0	0
T167	1015	0	0	0
T168	31640	0	0	0
T169	3851	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108340809	9799	0	0
T82	0	735	0	0
T96	0	1424	0	0
T103	74876	530	0	0
T116	0	775	0	0
T117	0	1095	0	0
T121	0	54	0	0
T127	0	1	0	0
T128	0	5	0	0
T159	0	4	0	0
T160	0	124	0	0
T161	13076	0	0	0
T162	21015	0	0	0
T163	1340	0	0	0
T164	4105	0	0	0
T165	578283	0	0	0
T166	53640	0	0	0
T167	1015	0	0	0
T168	31640	0	0	0
T169	3851	0	0	0