SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.61 | 100.00 | 90.48 | 97.60 | 100.00 | 100.00 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 53688697 | 53626146 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 53688697 | 53623950 | 0 | 789 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T32 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53688697 | 53626146 | 0 | 0 |
T1 | 54367 | 54287 | 0 | 0 |
T2 | 93029 | 92833 | 0 | 0 |
T3 | 90044 | 89006 | 0 | 0 |
T4 | 445465 | 445119 | 0 | 0 |
T5 | 206779 | 206469 | 0 | 0 |
T11 | 14855 | 14795 | 0 | 0 |
T12 | 162914 | 162851 | 0 | 0 |
T32 | 385392 | 385193 | 0 | 0 |
T33 | 3710 | 3628 | 0 | 0 |
T34 | 2068 | 2006 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 53688697 | 53623950 | 0 | 789 |
T1 | 54367 | 54284 | 0 | 3 |
T2 | 93029 | 92824 | 0 | 3 |
T3 | 90044 | 88988 | 0 | 3 |
T4 | 445465 | 445104 | 0 | 3 |
T5 | 206779 | 206451 | 0 | 3 |
T11 | 14855 | 14792 | 0 | 3 |
T12 | 162914 | 162848 | 0 | 3 |
T32 | 385392 | 385184 | 0 | 3 |
T33 | 3710 | 3625 | 0 | 3 |
T34 | 2068 | 2003 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |