Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : dmi_jtag_tap
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.77 100.00 100.00 92.50 98.57

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.dap.i_dmi_jtag_tap 98.12 100.00 100.00 92.50 100.00



Module Instance : tb.dut.dap.i_dmi_jtag_tap

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.12 100.00 100.00 92.50 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.50 100.00 100.00 92.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.81 94.32 90.57 100.00 82.35 dap


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_tck_inv 100.00 100.00 100.00 100.00

Line Coverage for Module : dmi_jtag_tap
Line No.TotalCoveredPercent
TOTAL9696100.00
ALWAYS791111100.00
ALWAYS10555100.00
ALWAYS1271515100.00
ALWAYS1511010100.00
ALWAYS17266100.00
ALWAYS20155100.00
ALWAYS2153131100.00
ALWAYS30277100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
79 1 1
80 1 1
83 1 1
84 1 1
MISSING_ELSE
88 1 1
89 1 1
MISSING_ELSE
93 1 1
94 1 1
MISSING_ELSE
97 1 1
99 1 1
100 1 1
MISSING_ELSE
105 1 1
106 1 1
107 1 1
109 1 1
110 1 1
127 1 1
128 1 1
130 1 1
131 2 2
MISSING_ELSE
132 2 2
MISSING_ELSE
MISSING_ELSE
135 1 1
136 2 2
MISSING_ELSE
137 2 2
MISSING_ELSE
MISSING_ELSE
140 1 1
142 1 1
143 1 1
MISSING_ELSE
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
172 1 1
173 1 1
176 1 1
177 1 1
178 1 1
179 1 1
201 1 1
202 1 1
203 1 1
205 1 1
206 1 1
215 1 1
217 1 1
218 1 1
219 1 1
221 1 1
222 1 1
224 1 1
226 1 1
228 1 1
229 1 1
232 1 1
236 1 1
239 1 1
240 1 1
243 1 1
244 1 1
247 1 1
250 1 1
253 1 1
256 1 1
257 1 1
261 1 1
268 1 1
269 1 1
276 1 1
277 1 1
280 1 1
284 1 1
287 1 1
294 1 1
295 1 1
302 1 1
303 1 1
304 1 1
305 1 1
307 1 1
308 1 1
309 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
320 1 1


Cond Coverage for Module : dmi_jtag_tap
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       206
 EXPRESSION (shift_ir | shift_dr)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       228
 EXPRESSION (tms_i ? TestLogicReset : RunTestIdle)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT94,T95,T96

 LINE       232
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (tms_i ? SelectIrScan : CaptureDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       240
 EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T96,T97

 LINE       244
 EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       247
 EXPRESSION (tms_i ? UpdateDr : PauseDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       250
 EXPRESSION (tms_i ? Exit2Dr : PauseDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       253
 EXPRESSION (tms_i ? UpdateDr : ShiftDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       261
 EXPRESSION (tms_i ? TestLogicReset : CaptureIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       269
 EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T32

 LINE       277
 EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       280
 EXPRESSION (tms_i ? UpdateIr : PauseIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       284
 EXPRESSION (tms_i ? Exit2Ir : PauseIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T33

 LINE       287
 EXPRESSION (tms_i ? UpdateIr : ShiftIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T33

 LINE       295
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Module : dmi_jtag_tap
Summary for FSM :: tap_state_q
TotalCoveredPercent
States 16 16 100.00 (Not included in score)
Transitions 40 37 92.50
Sequences 0 0

State, Transition and Sequence Details for FSM :: tap_state_q
statesLine No.CoveredTests
CaptureDr 236 Covered T1,T2,T3
CaptureIr 261 Covered T1,T2,T3
Exit1Dr 240 Covered T1,T2,T3
Exit1Ir 269 Covered T1,T2,T3
Exit2Dr 250 Covered T1,T2,T3
Exit2Ir 284 Covered T2,T3,T33
PauseDr 247 Covered T1,T2,T3
PauseIr 280 Covered T2,T3,T33
RunTestIdle 228 Covered T1,T2,T3
SelectDrScan 232 Covered T1,T2,T3
SelectIrScan 236 Covered T1,T2,T3
ShiftDr 240 Covered T1,T2,T3
ShiftIr 269 Covered T1,T2,T3
TestLogicReset 303 Covered T1,T2,T3
UpdateDr 247 Covered T1,T2,T3
UpdateIr 280 Covered T1,T2,T3


transitionsLine No.CoveredTests
CaptureDr->Exit1Dr 240 Covered T95,T96,T97
CaptureDr->ShiftDr 240 Covered T1,T2,T3
CaptureDr->TestLogicReset 303 Covered T98,T99,T100
CaptureIr->Exit1Ir 269 Covered T3,T5,T32
CaptureIr->ShiftIr 269 Covered T1,T2,T3
CaptureIr->TestLogicReset 303 Covered T100
Exit1Dr->PauseDr 247 Covered T1,T2,T3
Exit1Dr->TestLogicReset 303 Covered T101,T96,T63
Exit1Dr->UpdateDr 247 Covered T1,T2,T3
Exit1Ir->PauseIr 280 Covered T2,T3,T33
Exit1Ir->TestLogicReset 303 Covered T3
Exit1Ir->UpdateIr 280 Covered T1,T2,T3
Exit2Dr->ShiftDr 253 Covered T1,T2,T3
Exit2Dr->TestLogicReset 303 Covered T43,T56,T98
Exit2Dr->UpdateDr 253 Covered T1,T2,T3
Exit2Ir->ShiftIr 287 Covered T2,T3,T33
Exit2Ir->TestLogicReset 303 Covered T101
Exit2Ir->UpdateIr 287 Covered T3,T11,T4
PauseDr->Exit2Dr 250 Covered T1,T2,T3
PauseDr->TestLogicReset 303 Covered T3,T101,T102
PauseIr->Exit2Ir 284 Covered T2,T3,T33
PauseIr->TestLogicReset 303 Covered T3,T56,T82
RunTestIdle->SelectDrScan 232 Covered T1,T2,T3
RunTestIdle->TestLogicReset 303 Covered T2,T3,T4
SelectDrScan->CaptureDr 236 Covered T1,T2,T3
SelectDrScan->SelectIrScan 236 Covered T1,T2,T3
SelectDrScan->TestLogicReset 303 Covered T43,T102,T82
SelectIrScan->CaptureIr 261 Covered T1,T2,T3
SelectIrScan->TestLogicReset 303 Covered T3,T94,T95
ShiftDr->Exit1Dr 244 Covered T1,T2,T3
ShiftDr->TestLogicReset 303 Covered T5,T43,T103
ShiftIr->Exit1Ir 277 Covered T1,T2,T3
ShiftIr->TestLogicReset 303 Covered T104,T105,T106
TestLogicReset->RunTestIdle 228 Covered T1,T2,T3
UpdateDr->RunTestIdle 257 Covered T1,T2,T3
UpdateDr->SelectDrScan 257 Not Covered
UpdateDr->TestLogicReset 303 Covered T95
UpdateIr->RunTestIdle 295 Covered T1,T2,T3
UpdateIr->SelectDrScan 295 Not Covered
UpdateIr->TestLogicReset 303 Not Covered



Branch Coverage for Module : dmi_jtag_tap
Line No.TotalCoveredPercent
Branches 70 69 98.57
IF 83 2 2 100.00
IF 88 2 2 100.00
IF 93 2 2 100.00
IF 97 2 2 100.00
IF 105 2 2 100.00
IF 130 5 5 100.00
IF 135 5 5 100.00
IF 140 2 2 100.00
CASE 155 6 6 100.00
IF 172 5 5 100.00
IF 201 2 2 100.00
CASE 226 33 32 96.97
IF 302 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 if (shift_ir)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 88 if (capture_ir)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if (update_ir)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 97 if (test_logic_reset)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 105 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 130 if (capture_dr) -2-: 131 if (idcode_select) -3-: 132 if (bypass_select)

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 - Covered T1,T2,T3
1 - 1 Covered T1,T2,T3
1 - 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 135 if (shift_dr) -2-: 136 if (idcode_select) -3-: 137 if (bypass_select)

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 - Covered T1,T2,T3
1 - 1 Covered T1,T2,T3
1 - 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 140 if (test_logic_reset)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 case (jtag_ir_q)

Branches:
-1-StatusTests
BYPASS0 Covered T94,T95,T107
IDCODE Covered T1,T2,T3
DTMCSR Covered T2,T3,T4
DMIACCESS Covered T1,T2,T3
BYPASS1 Covered T107,T108,T109
default Covered T3,T5,T32


LineNo. Expression -1-: 172 if (shift_ir) -2-: 176 case (jtag_ir_q)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 IDCODE Covered T1,T2,T3
0 DTMCSR Covered T2,T3,T4
0 DMIACCESS Covered T1,T2,T3
0 default Covered T3,T5,T32


LineNo. Expression -1-: 201 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 226 case (tap_state_q) -2-: 228 (tms_i) ? -3-: 232 (tms_i) ? -4-: 236 (tms_i) ? -5-: 240 (tms_i) ? -6-: 244 (tms_i) ? -7-: 247 (tms_i) ? -8-: 250 (tms_i) ? -9-: 253 (tms_i) ? -10-: 257 (tms_i) ? -11-: 261 (tms_i) ? -12-: 269 (tms_i) ? -13-: 277 (tms_i) ? -14-: 280 (tms_i) ? -15-: 284 (tms_i) ? -16-: 287 (tms_i) ? -17-: 295 (tms_i) ?

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTests
TestLogicReset 1 - - - - - - - - - - - - - - - Covered T94,T95,T96
TestLogicReset 0 - - - - - - - - - - - - - - - Covered T1,T2,T3
RunTestIdle - 1 - - - - - - - - - - - - - - Covered T1,T2,T3
RunTestIdle - 0 - - - - - - - - - - - - - - Covered T1,T2,T3
SelectDrScan - - 1 - - - - - - - - - - - - - Covered T1,T2,T3
SelectDrScan - - 0 - - - - - - - - - - - - - Covered T1,T2,T3
CaptureDr - - - 1 - - - - - - - - - - - - Covered T95,T96,T97
CaptureDr - - - 0 - - - - - - - - - - - - Covered T1,T2,T3
ShiftDr - - - - 1 - - - - - - - - - - - Covered T1,T2,T3
ShiftDr - - - - 0 - - - - - - - - - - - Covered T1,T2,T3
Exit1Dr - - - - - 1 - - - - - - - - - - Covered T1,T2,T3
Exit1Dr - - - - - 0 - - - - - - - - - - Covered T1,T2,T3
PauseDr - - - - - - 1 - - - - - - - - - Covered T1,T2,T3
PauseDr - - - - - - 0 - - - - - - - - - Covered T1,T2,T3
Exit2Dr - - - - - - - 1 - - - - - - - - Covered T1,T2,T3
Exit2Dr - - - - - - - 0 - - - - - - - - Covered T1,T2,T3
UpdateDr - - - - - - - - 1 - - - - - - - Covered T1,T2,T3
UpdateDr - - - - - - - - 0 - - - - - - - Covered T1,T2,T3
SelectIrScan - - - - - - - - - 1 - - - - - - Covered T1,T2,T3
SelectIrScan - - - - - - - - - 0 - - - - - - Covered T1,T2,T3
CaptureIr - - - - - - - - - - 1 - - - - - Covered T3,T5,T32
CaptureIr - - - - - - - - - - 0 - - - - - Covered T1,T2,T3
ShiftIr - - - - - - - - - - - 1 - - - - Covered T1,T2,T3
ShiftIr - - - - - - - - - - - 0 - - - - Covered T1,T2,T3
Exit1Ir - - - - - - - - - - - - 1 - - - Covered T1,T2,T3
Exit1Ir - - - - - - - - - - - - 0 - - - Covered T1,T2,T3
PauseIr - - - - - - - - - - - - - 1 - - Covered T2,T3,T33
PauseIr - - - - - - - - - - - - - 0 - - Covered T1,T2,T3
Exit2Ir - - - - - - - - - - - - - - 1 - Covered T2,T3,T33
Exit2Ir - - - - - - - - - - - - - - 0 - Covered T1,T2,T3
UpdateIr - - - - - - - - - - - - - - - 1 Covered T1,T2,T3
UpdateIr - - - - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 302 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap
Line No.TotalCoveredPercent
TOTAL9696100.00
ALWAYS791111100.00
ALWAYS10555100.00
ALWAYS1271515100.00
ALWAYS1511010100.00
ALWAYS17266100.00
ALWAYS20155100.00
ALWAYS2153131100.00
ALWAYS30277100.00
CONT_ASSIGN31511100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
79 1 1
80 1 1
83 1 1
84 1 1
MISSING_ELSE
88 1 1
89 1 1
MISSING_ELSE
93 1 1
94 1 1
MISSING_ELSE
97 1 1
99 1 1
100 1 1
MISSING_ELSE
105 1 1
106 1 1
107 1 1
109 1 1
110 1 1
127 1 1
128 1 1
130 1 1
131 2 2
MISSING_ELSE
132 2 2
MISSING_ELSE
MISSING_ELSE
135 1 1
136 2 2
MISSING_ELSE
137 2 2
MISSING_ELSE
MISSING_ELSE
140 1 1
142 1 1
143 1 1
MISSING_ELSE
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
172 1 1
173 1 1
176 1 1
177 1 1
178 1 1
179 1 1
201 1 1
202 1 1
203 1 1
205 1 1
206 1 1
215 1 1
217 1 1
218 1 1
219 1 1
221 1 1
222 1 1
224 1 1
226 1 1
228 1 1
229 1 1
232 1 1
236 1 1
239 1 1
240 1 1
243 1 1
244 1 1
247 1 1
250 1 1
253 1 1
256 1 1
257 1 1
261 1 1
268 1 1
269 1 1
276 1 1
277 1 1
280 1 1
284 1 1
287 1 1
294 1 1
295 1 1
Exclude Annotation: VC_COV_UNR
302 1 1
303 1 1
304 1 1
305 1 1
307 1 1
308 1 1
309 1 1
315 1 1
316 1 1
317 1 1
318 1 1
319 1 1
320 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       206
 EXPRESSION (shift_ir | shift_dr)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       228
 EXPRESSION (tms_i ? TestLogicReset : RunTestIdle)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT94,T95,T96

 LINE       232
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (tms_i ? SelectIrScan : CaptureDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       240
 EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT95,T96,T97

 LINE       244
 EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       247
 EXPRESSION (tms_i ? UpdateDr : PauseDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       250
 EXPRESSION (tms_i ? Exit2Dr : PauseDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       253
 EXPRESSION (tms_i ? UpdateDr : ShiftDr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       261
 EXPRESSION (tms_i ? TestLogicReset : CaptureIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       269
 EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T32

 LINE       277
 EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       280
 EXPRESSION (tms_i ? UpdateIr : PauseIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       284
 EXPRESSION (tms_i ? Exit2Ir : PauseIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T33

 LINE       287
 EXPRESSION (tms_i ? UpdateIr : ShiftIr)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T33

 LINE       295
 EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap
Summary for FSM :: tap_state_q
TotalCoveredPercent
States 16 16 100.00 (Not included in score)
Transitions 40 37 92.50
Sequences 0 0

State, Transition and Sequence Details for FSM :: tap_state_q
statesLine No.CoveredTests
CaptureDr 236 Covered T1,T2,T3
CaptureIr 261 Covered T1,T2,T3
Exit1Dr 240 Covered T1,T2,T3
Exit1Ir 269 Covered T1,T2,T3
Exit2Dr 250 Covered T1,T2,T3
Exit2Ir 284 Covered T2,T3,T33
PauseDr 247 Covered T1,T2,T3
PauseIr 280 Covered T2,T3,T33
RunTestIdle 228 Covered T1,T2,T3
SelectDrScan 232 Covered T1,T2,T3
SelectIrScan 236 Covered T1,T2,T3
ShiftDr 240 Covered T1,T2,T3
ShiftIr 269 Covered T1,T2,T3
TestLogicReset 303 Covered T1,T2,T3
UpdateDr 247 Covered T1,T2,T3
UpdateIr 280 Covered T1,T2,T3


transitionsLine No.CoveredTests
CaptureDr->Exit1Dr 240 Covered T95,T96,T97
CaptureDr->ShiftDr 240 Covered T1,T2,T3
CaptureDr->TestLogicReset 303 Covered T98,T99,T100
CaptureIr->Exit1Ir 269 Covered T3,T5,T32
CaptureIr->ShiftIr 269 Covered T1,T2,T3
CaptureIr->TestLogicReset 303 Covered T100
Exit1Dr->PauseDr 247 Covered T1,T2,T3
Exit1Dr->TestLogicReset 303 Covered T101,T96,T63
Exit1Dr->UpdateDr 247 Covered T1,T2,T3
Exit1Ir->PauseIr 280 Covered T2,T3,T33
Exit1Ir->TestLogicReset 303 Covered T3
Exit1Ir->UpdateIr 280 Covered T1,T2,T3
Exit2Dr->ShiftDr 253 Covered T1,T2,T3
Exit2Dr->TestLogicReset 303 Covered T43,T56,T98
Exit2Dr->UpdateDr 253 Covered T1,T2,T3
Exit2Ir->ShiftIr 287 Covered T2,T3,T33
Exit2Ir->TestLogicReset 303 Covered T101
Exit2Ir->UpdateIr 287 Covered T3,T11,T4
PauseDr->Exit2Dr 250 Covered T1,T2,T3
PauseDr->TestLogicReset 303 Covered T3,T101,T102
PauseIr->Exit2Ir 284 Covered T2,T3,T33
PauseIr->TestLogicReset 303 Covered T3,T56,T82
RunTestIdle->SelectDrScan 232 Covered T1,T2,T3
RunTestIdle->TestLogicReset 303 Covered T2,T3,T4
SelectDrScan->CaptureDr 236 Covered T1,T2,T3
SelectDrScan->SelectIrScan 236 Covered T1,T2,T3
SelectDrScan->TestLogicReset 303 Covered T43,T102,T82
SelectIrScan->CaptureIr 261 Covered T1,T2,T3
SelectIrScan->TestLogicReset 303 Covered T3,T94,T95
ShiftDr->Exit1Dr 244 Covered T1,T2,T3
ShiftDr->TestLogicReset 303 Covered T5,T43,T103
ShiftIr->Exit1Ir 277 Covered T1,T2,T3
ShiftIr->TestLogicReset 303 Covered T104,T105,T106
TestLogicReset->RunTestIdle 228 Covered T1,T2,T3
UpdateDr->RunTestIdle 257 Covered T1,T2,T3
UpdateDr->SelectDrScan 257 Not Covered
UpdateDr->TestLogicReset 303 Covered T95
UpdateIr->RunTestIdle 295 Covered T1,T2,T3
UpdateIr->SelectDrScan 295 Not Covered
UpdateIr->TestLogicReset 303 Not Covered



Branch Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap
Line No.TotalCoveredPercent
Branches 69 69 100.00
IF 83 2 2 100.00
IF 88 2 2 100.00
IF 93 2 2 100.00
IF 97 2 2 100.00
IF 105 2 2 100.00
IF 130 5 5 100.00
IF 135 5 5 100.00
IF 140 2 2 100.00
CASE 155 6 6 100.00
IF 172 5 5 100.00
IF 201 2 2 100.00
CASE 226 32 32 100.00
IF 302 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 83 if (shift_ir)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 88 if (capture_ir)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 93 if (update_ir)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 97 if (test_logic_reset)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 105 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 130 if (capture_dr) -2-: 131 if (idcode_select) -3-: 132 if (bypass_select)

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 - Covered T1,T2,T3
1 - 1 Covered T1,T2,T3
1 - 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 135 if (shift_dr) -2-: 136 if (idcode_select) -3-: 137 if (bypass_select)

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T3
1 0 - Covered T1,T2,T3
1 - 1 Covered T1,T2,T3
1 - 0 Covered T1,T2,T3
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 140 if (test_logic_reset)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 155 case (jtag_ir_q)

Branches:
-1-StatusTests
BYPASS0 Covered T94,T95,T107
IDCODE Covered T1,T2,T3
DTMCSR Covered T2,T3,T4
DMIACCESS Covered T1,T2,T3
BYPASS1 Covered T107,T108,T109
default Covered T3,T5,T32


LineNo. Expression -1-: 172 if (shift_ir) -2-: 176 case (jtag_ir_q)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 IDCODE Covered T1,T2,T3
0 DTMCSR Covered T2,T3,T4
0 DMIACCESS Covered T1,T2,T3
0 default Covered T3,T5,T32


LineNo. Expression -1-: 201 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 226 case (tap_state_q) -2-: 228 (tms_i) ? -3-: 232 (tms_i) ? -4-: 236 (tms_i) ? -5-: 240 (tms_i) ? -6-: 244 (tms_i) ? -7-: 247 (tms_i) ? -8-: 250 (tms_i) ? -9-: 253 (tms_i) ? -10-: 257 (tms_i) ? -11-: 261 (tms_i) ? -12-: 269 (tms_i) ? -13-: 277 (tms_i) ? -14-: 280 (tms_i) ? -15-: 284 (tms_i) ? -16-: 287 (tms_i) ? -17-: 295 (tms_i) ?

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTestsExclude Annotation
TestLogicReset 1 - - - - - - - - - - - - - - - Covered T94,T95,T96
TestLogicReset 0 - - - - - - - - - - - - - - - Covered T1,T2,T3
RunTestIdle - 1 - - - - - - - - - - - - - - Covered T1,T2,T3
RunTestIdle - 0 - - - - - - - - - - - - - - Covered T1,T2,T3
SelectDrScan - - 1 - - - - - - - - - - - - - Covered T1,T2,T3
SelectDrScan - - 0 - - - - - - - - - - - - - Covered T1,T2,T3
CaptureDr - - - 1 - - - - - - - - - - - - Covered T95,T96,T97
CaptureDr - - - 0 - - - - - - - - - - - - Covered T1,T2,T3
ShiftDr - - - - 1 - - - - - - - - - - - Covered T1,T2,T3
ShiftDr - - - - 0 - - - - - - - - - - - Covered T1,T2,T3
Exit1Dr - - - - - 1 - - - - - - - - - - Covered T1,T2,T3
Exit1Dr - - - - - 0 - - - - - - - - - - Covered T1,T2,T3
PauseDr - - - - - - 1 - - - - - - - - - Covered T1,T2,T3
PauseDr - - - - - - 0 - - - - - - - - - Covered T1,T2,T3
Exit2Dr - - - - - - - 1 - - - - - - - - Covered T1,T2,T3
Exit2Dr - - - - - - - 0 - - - - - - - - Covered T1,T2,T3
UpdateDr - - - - - - - - 1 - - - - - - - Covered T1,T2,T3
UpdateDr - - - - - - - - 0 - - - - - - - Covered T1,T2,T3
SelectIrScan - - - - - - - - - 1 - - - - - - Covered T1,T2,T3
SelectIrScan - - - - - - - - - 0 - - - - - - Covered T1,T2,T3
CaptureIr - - - - - - - - - - 1 - - - - - Covered T3,T5,T32
CaptureIr - - - - - - - - - - 0 - - - - - Covered T1,T2,T3
ShiftIr - - - - - - - - - - - 1 - - - - Covered T1,T2,T3
ShiftIr - - - - - - - - - - - 0 - - - - Covered T1,T2,T3
Exit1Ir - - - - - - - - - - - - 1 - - - Covered T1,T2,T3
Exit1Ir - - - - - - - - - - - - 0 - - - Covered T1,T2,T3
PauseIr - - - - - - - - - - - - - 1 - - Covered T2,T3,T33
PauseIr - - - - - - - - - - - - - 0 - - Covered T1,T2,T3
Exit2Ir - - - - - - - - - - - - - - 1 - Covered T2,T3,T33
Exit2Ir - - - - - - - - - - - - - - 0 - Covered T1,T2,T3
UpdateIr - - - - - - - - - - - - - - - 1 Covered T1,T2,T3
UpdateIr - - - - - - - - - - - - - - - 0 Covered T1,T2,T3
default - - - - - - - - - - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 302 if ((!trst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%