Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
1 | 1 | Covered | T94 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T94 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7419276 |
7417784 |
0 |
0 |
selKnown1 |
58741036 |
58739544 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7419276 |
7417784 |
0 |
0 |
T1 |
28232 |
28230 |
0 |
0 |
T2 |
14582 |
14578 |
0 |
0 |
T3 |
11135 |
11131 |
0 |
0 |
T4 |
28212 |
28208 |
0 |
0 |
T5 |
69219 |
69215 |
0 |
0 |
T9 |
0 |
7 |
0 |
0 |
T11 |
1370 |
1366 |
0 |
0 |
T12 |
18274 |
18270 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
20 |
0 |
0 |
T29 |
2 |
0 |
0 |
0 |
T32 |
18635 |
18631 |
0 |
0 |
T33 |
358 |
354 |
0 |
0 |
T34 |
282 |
278 |
0 |
0 |
T37 |
0 |
9 |
0 |
0 |
T65 |
0 |
2 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58741036 |
58739544 |
0 |
0 |
T1 |
68483 |
68481 |
0 |
0 |
T2 |
100323 |
100319 |
0 |
0 |
T3 |
95617 |
95613 |
0 |
0 |
T4 |
459574 |
459570 |
0 |
0 |
T5 |
241395 |
241391 |
0 |
0 |
T9 |
0 |
6 |
0 |
0 |
T11 |
15541 |
15537 |
0 |
0 |
T12 |
172052 |
172048 |
0 |
0 |
T25 |
0 |
6 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
20 |
0 |
0 |
T29 |
2 |
0 |
0 |
0 |
T32 |
394712 |
394708 |
0 |
0 |
T33 |
3890 |
3886 |
0 |
0 |
T34 |
2210 |
2206 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
1 | 1 | Covered | T94 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T94 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2366836 |
2366573 |
0 |
0 |
selKnown1 |
53688697 |
53688434 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2366836 |
2366573 |
0 |
0 |
T1 |
14116 |
14115 |
0 |
0 |
T2 |
7288 |
7287 |
0 |
0 |
T3 |
5561 |
5560 |
0 |
0 |
T4 |
14099 |
14098 |
0 |
0 |
T5 |
34604 |
34603 |
0 |
0 |
T11 |
684 |
683 |
0 |
0 |
T12 |
9136 |
9135 |
0 |
0 |
T32 |
9314 |
9313 |
0 |
0 |
T33 |
178 |
177 |
0 |
0 |
T34 |
140 |
139 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
53688697 |
53688434 |
0 |
0 |
T1 |
54367 |
54366 |
0 |
0 |
T2 |
93029 |
93028 |
0 |
0 |
T3 |
90044 |
90043 |
0 |
0 |
T4 |
445465 |
445464 |
0 |
0 |
T5 |
206779 |
206778 |
0 |
0 |
T11 |
14855 |
14854 |
0 |
0 |
T12 |
162914 |
162913 |
0 |
0 |
T32 |
385392 |
385391 |
0 |
0 |
T33 |
3710 |
3709 |
0 |
0 |
T34 |
2068 |
2067 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
1 | 1 | Covered | T94 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T94 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
778 |
515 |
0 |
0 |
T2 |
3 |
2 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T32 |
3 |
2 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
732 |
469 |
0 |
0 |
T2 |
3 |
2 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T32 |
3 |
2 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
1 | 1 | Covered | T94 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T94 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5049875 |
5049392 |
0 |
0 |
selKnown1 |
5049874 |
5049391 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5049875 |
5049392 |
0 |
0 |
T1 |
14116 |
14115 |
0 |
0 |
T2 |
7288 |
7287 |
0 |
0 |
T3 |
5561 |
5560 |
0 |
0 |
T4 |
14099 |
14098 |
0 |
0 |
T5 |
34604 |
34603 |
0 |
0 |
T11 |
684 |
683 |
0 |
0 |
T12 |
9136 |
9135 |
0 |
0 |
T32 |
9314 |
9313 |
0 |
0 |
T33 |
178 |
177 |
0 |
0 |
T34 |
140 |
139 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5049874 |
5049391 |
0 |
0 |
T1 |
14116 |
14115 |
0 |
0 |
T2 |
7288 |
7287 |
0 |
0 |
T3 |
5561 |
5560 |
0 |
0 |
T4 |
14099 |
14098 |
0 |
0 |
T5 |
34604 |
34603 |
0 |
0 |
T11 |
684 |
683 |
0 |
0 |
T12 |
9136 |
9135 |
0 |
0 |
T32 |
9314 |
9313 |
0 |
0 |
T33 |
178 |
177 |
0 |
0 |
T34 |
140 |
139 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T94 |
1 | 1 | Covered | T94 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T94 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1787 |
1304 |
0 |
0 |
selKnown1 |
1733 |
1250 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1787 |
1304 |
0 |
0 |
T2 |
3 |
2 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T32 |
4 |
3 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T37 |
0 |
5 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1733 |
1250 |
0 |
0 |
T2 |
3 |
2 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T11 |
1 |
0 |
0 |
0 |
T12 |
1 |
0 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T27 |
0 |
2 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T32 |
3 |
2 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
T34 |
1 |
0 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |