Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 100.00 66.67 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 100.00 66.67 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 87.50 100.00 i_cdc_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_rz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 100.00 66.67 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 100.00 66.67 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.78 100.00 93.33 100.00 i_cdc_resp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_rz_hs_protocol.req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN5500
ALWAYS751010100.00
ALWAYS11733100.00
ALWAYS1261111100.00
ALWAYS16933100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
75 1 1
76 1 1
77 1 1
79 1 1
83 1 1
84 1 1
MISSING_ELSE
88 1 1
90 1 1
93 1 1
94 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
126 1 1
127 1 1
128 1 1
130 1 1
132 1 1
134 1 1
137 1 1
138 1 1
MISSING_ELSE
MISSING_ELSE
143 1 1
145 1 1
146 1 1
MISSING_ELSE
169 1 1
170 1 1
172 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 13 13 100.00
CASE 79 4 4 100.00
IF 117 2 2 100.00
CASE 130 5 5 100.00
IF 169 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 79 case (gen_rz_hs_protocol.src_fsm_q) -2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i)) -3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:
-1--2--3-StatusTests
LoSt 1 - Covered T1,T2,T3
LoSt 0 - Covered T1,T2,T3
HiSt - 1 Covered T1,T2,T3
HiSt - 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 130 case (gen_rz_hs_protocol.dst_fsm_q) -2-: 132 if (gen_rz_hs_protocol.dst_req) -3-: 137 if (dst_ack_i) -4-: 145 if ((!gen_rz_hs_protocol.dst_req))

Branches:
-1--2--3--4-StatusTests
LoSt 1 1 - Covered T1,T2,T3
LoSt 1 0 - Covered T1,T2,T3
LoSt 0 - - Covered T1,T2,T3
HiSt - - 1 Covered T1,T2,T3
HiSt - - 0 Covered T1,T2,T3


LineNo. Expression -1-: 169 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 113390683 85430 0 0
SyncReqAckHoldReq 113390683 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 113390683 85430 0 0
T1 68483 252 0 0
T2 100317 130 0 0
T3 95605 88 0 0
T4 459564 236 0 0
T5 241383 534 0 0
T11 15539 12 0 0
T12 172050 164 0 0
T32 394706 150 0 0
T33 3888 2 0 0
T34 2208 2 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 113390683 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN5500
ALWAYS751010100.00
ALWAYS11733100.00
ALWAYS1261111100.00
ALWAYS16933100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
75 1 1
76 1 1
77 1 1
79 1 1
83 1 1
84 1 1
MISSING_ELSE
88 1 1
90 1 1
93 1 1
94 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
126 1 1
127 1 1
128 1 1
130 1 1
132 1 1
134 1 1
137 1 1
138 1 1
MISSING_ELSE
MISSING_ELSE
143 1 1
145 1 1
146 1 1
MISSING_ELSE
169 1 1
170 1 1
172 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
Line No.TotalCoveredPercent
Branches 13 13 100.00
CASE 79 4 4 100.00
IF 117 2 2 100.00
CASE 130 5 5 100.00
IF 169 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 79 case (gen_rz_hs_protocol.src_fsm_q) -2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i)) -3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:
-1--2--3-StatusTests
LoSt 1 - Covered T1,T2,T3
LoSt 0 - Covered T1,T2,T3
HiSt - 1 Covered T1,T2,T3
HiSt - 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 130 case (gen_rz_hs_protocol.dst_fsm_q) -2-: 132 if (gen_rz_hs_protocol.dst_req) -3-: 137 if (dst_ack_i) -4-: 145 if ((!gen_rz_hs_protocol.dst_req))

Branches:
-1--2--3--4-StatusTests
LoSt 1 1 - Covered T1,T2,T3
LoSt 1 0 - Covered T1,T2,T3
LoSt 0 - - Covered T1,T2,T3
HiSt - - 1 Covered T1,T2,T3
HiSt - - 0 Covered T1,T2,T3


LineNo. Expression -1-: 169 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 108340809 42716 0 0
SyncReqAckHoldReq 5049874 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 108340809 42716 0 0
T1 54367 126 0 0
T2 93029 65 0 0
T3 90044 44 0 0
T4 445465 118 0 0
T5 206779 267 0 0
T11 14855 6 0 0
T12 162914 82 0 0
T32 385392 75 0 0
T33 3710 1 0 0
T34 2068 1 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 5049874 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN5500
ALWAYS751010100.00
ALWAYS11733100.00
ALWAYS1261111100.00
ALWAYS16933100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
75 1 1
76 1 1
77 1 1
79 1 1
83 1 1
84 1 1
MISSING_ELSE
88 1 1
90 1 1
93 1 1
94 1 1
MISSING_ELSE
117 1 1
118 1 1
120 1 1
126 1 1
127 1 1
128 1 1
130 1 1
132 1 1
134 1 1
137 1 1
138 1 1
==> MISSING_ELSE
MISSING_ELSE
143 1 1
145 1 1
146 1 1
MISSING_ELSE
169 1 1
170 1 1
172 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 79 4 4 100.00
IF 117 2 2 100.00
CASE 130 4 4 100.00
IF 169 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 79 case (gen_rz_hs_protocol.src_fsm_q) -2-: 83 if (((!gen_rz_hs_protocol.src_ack) && src_req_i)) -3-: 93 if (((!src_req_i) || gen_rz_hs_protocol.src_ack))

Branches:
-1--2--3-StatusTests
LoSt 1 - Covered T1,T2,T3
LoSt 0 - Covered T1,T2,T3
HiSt - 1 Covered T1,T2,T3
HiSt - 0 Covered T1,T2,T3


LineNo. Expression -1-: 117 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 130 case (gen_rz_hs_protocol.dst_fsm_q) -2-: 132 if (gen_rz_hs_protocol.dst_req) -3-: 137 if (dst_ack_i) -4-: 145 if ((!gen_rz_hs_protocol.dst_req))

Branches:
-1--2--3--4-StatusTestsExclude Annotation
LoSt 1 1 - Covered T1,T2,T3
LoSt 1 0 - Excluded VC_COV_UNR
LoSt 0 - - Covered T1,T2,T3
HiSt - - 1 Covered T1,T2,T3
HiSt - - 0 Covered T1,T2,T3


LineNo. Expression -1-: 169 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 5049874 42714 0 0
SyncReqAckHoldReq 108340809 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 5049874 42714 0 0
T1 14116 126 0 0
T2 7288 65 0 0
T3 5561 44 0 0
T4 14099 118 0 0
T5 34604 267 0 0
T11 684 6 0 0
T12 9136 82 0 0
T32 9314 75 0 0
T33 178 1 0 0
T34 140 1 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 108340809 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%