Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	254870	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

579417

1

T7

1

T8

3

T9

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	463888	1			T8	3		T9	3		T4	7
values[0x0]	155708	1			T7	1		T8	4		T9	5
values[0x1]	214691	1			T7	1		T9	2		T4	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	167073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

667214

1

T7

1

T8

5

T9

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3100	1			T21	16		T186	3		T12	23
valid_sources[0x01]	2799	1			T21	6		T95	1		T12	27
valid_sources[0x02]	3059	1			T21	40		T12	52		T46	58
valid_sources[0x03]	3360	1			T21	26		T13	41		T61	2
valid_sources[0x04]	2999	1			T21	36		T160	3		T12	21
valid_sources[0x05]	3017	1			T21	64		T12	40		T46	16
valid_sources[0x06]	3410	1			T21	60		T13	143		T11	1
valid_sources[0x07]	3502	1			T21	16		T13	117		T12	45
valid_sources[0x08]	3776	1			T21	38		T13	25		T12	32
valid_sources[0x09]	3022	1			T21	20		T12	44		T46	12
valid_sources[0x0a]	2973	1			T27	2		T21	59		T10	2
valid_sources[0x0b]	3110	1			T21	52		T13	134		T12	45
valid_sources[0x0c]	2831	1			T21	36		T42	3		T12	48
valid_sources[0x0d]	2982	1			T21	21		T13	34		T12	42
valid_sources[0x0e]	3310	1			T21	43		T12	31		T46	55
valid_sources[0x0f]	3521	1			T21	13		T10	1		T13	52
valid_sources[0x10]	3124	1			T21	6		T12	24		T46	38
valid_sources[0x11]	3122	1			T21	44		T13	44		T44	2
valid_sources[0x12]	3415	1			T21	44		T13	434		T12	32
valid_sources[0x13]	3169	1			T21	36		T15	1		T12	53
valid_sources[0x14]	2992	1			T21	21		T13	69		T12	42
valid_sources[0x15]	3274	1			T4	2		T21	47		T12	50
valid_sources[0x16]	2890	1			T9	1		T21	65		T12	38
valid_sources[0x17]	2958	1			T21	47		T12	41		T46	24
valid_sources[0x18]	5136	1			T21	46		T13	19		T12	36
valid_sources[0x19]	3186	1			T21	32		T13	41		T12	59
valid_sources[0x1a]	3834	1			T21	28		T12	40		T46	55
valid_sources[0x1b]	3692	1			T21	31		T13	135		T12	46
valid_sources[0x1c]	2905	1			T4	1		T21	9		T12	41
valid_sources[0x1d]	2937	1			T21	35		T13	61		T40	3
valid_sources[0x1e]	3522	1			T21	18		T11	1		T12	50
valid_sources[0x1f]	3115	1			T21	54		T13	111		T12	43
valid_sources[0x20]	3158	1			T21	24		T13	11		T12	44
valid_sources[0x21]	3091	1			T9	1		T21	57		T13	91
valid_sources[0x22]	3003	1			T21	47		T13	60		T43	1
valid_sources[0x23]	2906	1			T21	38		T13	261		T12	38
valid_sources[0x24]	3907	1			T21	28		T13	359		T12	48
valid_sources[0x25]	3801	1			T21	60		T13	20		T12	41
valid_sources[0x26]	3441	1			T39	1		T21	17		T13	25
valid_sources[0x27]	2865	1			T21	17		T13	155		T12	39
valid_sources[0x28]	2970	1			T21	20		T13	69		T40	8
valid_sources[0x29]	3158	1			T21	22		T12	35		T46	54
valid_sources[0x2a]	2963	1			T21	12		T13	45		T40	1
valid_sources[0x2b]	3270	1			T9	2		T21	46		T13	135
valid_sources[0x2c]	3382	1			T21	11		T13	100		T42	7
valid_sources[0x2d]	3393	1			T21	35		T13	29		T169	1
valid_sources[0x2e]	2860	1			T21	74		T13	162		T12	33
valid_sources[0x2f]	2644	1			T21	19		T13	67		T12	37
valid_sources[0x30]	3112	1			T21	25		T10	1		T30	3
valid_sources[0x31]	3054	1			T21	7		T11	1		T12	32
valid_sources[0x32]	2941	1			T21	110		T40	3		T12	36
valid_sources[0x33]	3253	1			T9	2		T21	15		T13	58
valid_sources[0x34]	3027	1			T21	64		T61	5		T12	32
valid_sources[0x35]	2760	1			T21	46		T13	45		T12	39
valid_sources[0x36]	3310	1			T21	32		T13	35		T44	7
valid_sources[0x37]	3981	1			T21	22		T40	4		T12	34
valid_sources[0x38]	2830	1			T21	74		T13	129		T40	2
valid_sources[0x39]	3740	1			T21	38		T10	1		T13	23
valid_sources[0x3a]	3383	1			T21	53		T13	8		T12	30
valid_sources[0x3b]	3131	1			T21	3		T13	62		T40	1
valid_sources[0x3c]	8572	1			T21	28		T13	53		T12	44
valid_sources[0x3d]	3325	1			T21	34		T13	4		T187	2
valid_sources[0x3e]	3044	1			T21	37		T13	151		T12	41
valid_sources[0x3f]	2999	1			T21	13		T10	1		T163	2
valid_sources[0x40]	3564	1			T4	1		T21	22		T13	162
valid_sources[0x41]	3294	1			T21	34		T13	243		T12	40
valid_sources[0x42]	2834	1			T21	40		T12	41		T46	29
valid_sources[0x43]	3077	1			T21	17		T13	212		T12	52
valid_sources[0x44]	2859	1			T21	62		T12	38		T46	30
valid_sources[0x45]	3220	1			T21	31		T13	14		T12	45
valid_sources[0x46]	2825	1			T21	72		T13	76		T11	1
valid_sources[0x47]	2939	1			T4	2		T21	3		T12	28
valid_sources[0x48]	5712	1			T21	50		T13	111		T12	43
valid_sources[0x49]	3645	1			T21	20		T10	1		T13	58
valid_sources[0x4a]	2635	1			T21	46		T13	117		T12	28
valid_sources[0x4b]	2944	1			T6	1		T21	23		T12	35
valid_sources[0x4c]	2770	1			T21	18		T13	147		T12	37
valid_sources[0x4d]	3441	1			T4	3		T21	58		T10	1
valid_sources[0x4e]	3637	1			T21	19		T30	2		T12	34
valid_sources[0x4f]	4679	1			T21	61		T10	1		T40	5
valid_sources[0x50]	3621	1			T21	40		T12	48		T46	142
valid_sources[0x51]	3237	1			T21	86		T12	28		T46	65
valid_sources[0x52]	3607	1			T21	72		T12	44		T46	65
valid_sources[0x53]	3033	1			T21	20		T13	135		T12	48
valid_sources[0x54]	2380	1			T21	18		T12	40		T46	45
valid_sources[0x55]	2844	1			T21	10		T13	35		T14	7
valid_sources[0x56]	2888	1			T21	25		T13	10		T12	48
valid_sources[0x57]	3766	1			T21	2		T13	195		T12	27
valid_sources[0x58]	2992	1			T21	102		T18	1		T13	27
valid_sources[0x59]	3338	1			T21	181		T10	1		T13	22
valid_sources[0x5a]	3245	1			T21	139		T12	22		T46	2
valid_sources[0x5b]	3151	1			T39	1		T21	74		T40	3
valid_sources[0x5c]	3047	1			T21	115		T12	34		T46	30
valid_sources[0x5d]	4458	1			T21	57		T13	254		T12	43
valid_sources[0x5e]	3035	1			T21	34		T13	3		T12	35
valid_sources[0x5f]	3311	1			T21	26		T13	17		T12	35
valid_sources[0x60]	3283	1			T21	20		T13	73		T12	51
valid_sources[0x61]	2983	1			T9	1		T21	17		T13	86
valid_sources[0x62]	2994	1			T21	24		T13	100		T12	31
valid_sources[0x63]	3867	1			T21	31		T13	19		T43	1
valid_sources[0x64]	3195	1			T21	21		T188	3		T12	41
valid_sources[0x65]	2826	1			T21	11		T13	162		T12	30
valid_sources[0x66]	3041	1			T21	79		T13	30		T15	1
valid_sources[0x67]	2827	1			T21	30		T12	54		T46	21
valid_sources[0x68]	3083	1			T21	37		T13	62		T12	50
valid_sources[0x69]	2693	1			T21	48		T13	9		T12	34
valid_sources[0x6a]	3020	1			T21	62		T13	29		T12	39
valid_sources[0x6b]	3150	1			T21	34		T12	28		T46	38
valid_sources[0x6c]	3071	1			T21	50		T13	138		T12	42
valid_sources[0x6d]	3354	1			T21	51		T12	41		T46	66
valid_sources[0x6e]	3381	1			T21	31		T13	68		T12	34
valid_sources[0x6f]	2902	1			T21	48		T58	2		T12	28
valid_sources[0x70]	3322	1			T21	25		T10	1		T40	5
valid_sources[0x71]	6934	1			T21	16		T13	26		T43	1
valid_sources[0x72]	2802	1			T21	32		T13	24		T12	46
valid_sources[0x73]	4210	1			T21	82		T13	178		T189	5
valid_sources[0x74]	3693	1			T6	1		T21	19		T13	42
valid_sources[0x75]	3423	1			T21	37		T13	94		T43	1
valid_sources[0x76]	3209	1			T21	27		T13	81		T42	3
valid_sources[0x77]	2999	1			T21	93		T12	32		T46	50
valid_sources[0x78]	3230	1			T21	29		T13	5		T40	2
valid_sources[0x79]	3006	1			T21	42		T13	28		T45	1
valid_sources[0x7a]	3092	1			T21	36		T10	1		T12	46
valid_sources[0x7b]	2800	1			T21	34		T13	8		T12	40
valid_sources[0x7c]	3067	1			T21	35		T13	233		T40	3
valid_sources[0x7d]	3546	1			T21	34		T13	215		T12	39
valid_sources[0x7e]	2852	1			T21	32		T13	28		T40	6
valid_sources[0x7f]	3362	1			T9	1		T21	15		T13	1
valid_sources[0x80]	2718	1			T21	42		T12	46		T46	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

283605

1

T8

1

T9

2

T4

3

values[0x0]

all_enables

biggest_size

147985

1

T8

2

T9

3

T5

2

values[0x1]

all_enables

biggest_size

147827

1

T7

1

T9

1

T21

1873

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8132	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115155

1

T1

6

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34203	1			T21	1817		T13	1901		T12	1583
values[0x0]	43227	1			T1	4		T2	1		T3	1
values[0x1]	45857	1			T1	2		T7	1		T9	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

118092

1

T1

6

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	638	1			T12	14		T19	24		T190	1
valid_sources[0x01]	357	1			T66	1		T12	168		T84	9
valid_sources[0x02]	389	1			T21	32		T100	2		T12	6
valid_sources[0x03]	392	1			T21	69		T87	1		T19	24
valid_sources[0x04]	314	1			T21	1		T12	2		T22	1
valid_sources[0x05]	202	1			T21	2		T10	1		T13	1
valid_sources[0x06]	716	1			T21	3		T14	2		T191	1
valid_sources[0x07]	334	1			T21	2		T13	1		T192	2
valid_sources[0x08]	489	1			T31	1		T46	163		T19	32
valid_sources[0x09]	467	1			T21	109		T12	3		T71	1
valid_sources[0x0a]	161	1			T1	1		T82	1		T193	1
valid_sources[0x0b]	506	1			T46	263		T194	2		T84	33
valid_sources[0x0c]	494	1			T10	1		T12	162		T195	1
valid_sources[0x0d]	580	1			T21	1		T10	4		T13	123
valid_sources[0x0e]	312	1			T196	1		T19	16		T47	118
valid_sources[0x0f]	621	1			T13	5		T17	1		T12	2
valid_sources[0x10]	252	1			T197	1		T12	1		T84	1
valid_sources[0x11]	373	1			T84	3		T19	24		T198	1
valid_sources[0x12]	402	1			T33	1		T21	1		T12	1
valid_sources[0x13]	372	1			T160	2		T12	2		T84	1
valid_sources[0x14]	599	1			T21	1		T12	173		T46	202
valid_sources[0x15]	757	1			T21	205		T10	1		T199	2
valid_sources[0x16]	328	1			T21	47		T12	83		T75	2
valid_sources[0x17]	797	1			T21	1		T87	70		T19	12
valid_sources[0x18]	876	1			T21	1		T192	2		T12	170
valid_sources[0x19]	250	1			T15	7		T12	3		T19	25
valid_sources[0x1a]	265	1			T26	1		T13	1		T197	1
valid_sources[0x1b]	607	1			T39	3		T21	1		T13	79
valid_sources[0x1c]	684	1			T21	3		T13	53		T200	3
valid_sources[0x1d]	304	1			T13	1		T12	24		T87	80
valid_sources[0x1e]	295	1			T27	1		T21	1		T201	1
valid_sources[0x1f]	648	1			T12	2		T46	201		T19	14
valid_sources[0x20]	258	1			T19	29		T53	1		T85	1
valid_sources[0x21]	563	1			T202	1		T12	1		T87	65
valid_sources[0x22]	334	1			T60	1		T21	4		T87	100
valid_sources[0x23]	464	1			T12	81		T19	19		T203	1
valid_sources[0x24]	278	1			T87	1		T84	15		T19	15
valid_sources[0x25]	806	1			T204	1		T12	1		T46	429
valid_sources[0x26]	308	1			T21	83		T205	3		T161	1
valid_sources[0x27]	363	1			T13	57		T206	1		T196	1
valid_sources[0x28]	908	1			T21	1		T13	134		T12	3
valid_sources[0x29]	336	1			T5	1		T21	1		T40	1
valid_sources[0x2a]	843	1			T21	1		T13	271		T207	2
valid_sources[0x2b]	229	1			T14	1		T12	1		T164	2
valid_sources[0x2c]	526	1			T21	15		T46	1		T19	28
valid_sources[0x2d]	750	1			T29	1		T21	128		T208	1
valid_sources[0x2e]	722	1			T21	66		T13	1		T186	1
valid_sources[0x2f]	535	1			T21	2		T209	7		T12	4
valid_sources[0x30]	464	1			T13	134		T71	1		T87	2
valid_sources[0x31]	250	1			T12	1		T164	3		T87	1
valid_sources[0x32]	563	1			T21	3		T196	1		T84	39
valid_sources[0x33]	392	1			T21	1		T13	3		T19	15
valid_sources[0x34]	848	1			T21	6		T13	102		T11	2
valid_sources[0x35]	452	1			T210	1		T204	1		T19	19
valid_sources[0x36]	383	1			T21	40		T17	2		T211	3
valid_sources[0x37]	293	1			T65	1		T189	4		T192	1
valid_sources[0x38]	574	1			T60	1		T12	1		T87	1
valid_sources[0x39]	270	1			T21	1		T13	3		T169	8
valid_sources[0x3a]	229	1			T33	1		T21	3		T12	2
valid_sources[0x3b]	819	1			T21	1		T13	149		T12	111
valid_sources[0x3c]	260	1			T204	2		T46	1		T19	6
valid_sources[0x3d]	710	1			T21	142		T46	177		T87	76
valid_sources[0x3e]	301	1			T19	17		T85	7		T99	10
valid_sources[0x3f]	495	1			T21	89		T12	4		T19	23
valid_sources[0x40]	445	1			T165	1		T84	52		T19	25
valid_sources[0x41]	1314	1			T21	176		T13	136		T159	1
valid_sources[0x42]	694	1			T21	4		T12	99		T19	16
valid_sources[0x43]	594	1			T21	49		T30	1		T12	101
valid_sources[0x44]	299	1			T21	1		T12	1		T212	2
valid_sources[0x45]	288	1			T31	1		T205	1		T213	1
valid_sources[0x46]	415	1			T67	1		T13	137		T12	1
valid_sources[0x47]	476	1			T33	1		T21	2		T17	2
valid_sources[0x48]	309	1			T201	5		T199	1		T42	1
valid_sources[0x49]	538	1			T12	54		T164	2		T19	20
valid_sources[0x4a]	278	1			T21	101		T196	1		T42	2
valid_sources[0x4b]	382	1			T4	6		T17	1		T205	2
valid_sources[0x4c]	345	1			T21	1		T68	1		T13	1
valid_sources[0x4d]	463	1			T1	1		T12	110		T214	1
valid_sources[0x4e]	642	1			T21	1		T12	1		T46	176
valid_sources[0x4f]	429	1			T66	2		T61	2		T192	4
valid_sources[0x50]	421	1			T52	1		T12	187		T19	15
valid_sources[0x51]	875	1			T13	6		T215	1		T12	47
valid_sources[0x52]	1188	1			T21	217		T42	1		T12	4
valid_sources[0x53]	480	1			T13	111		T12	2		T19	28
valid_sources[0x54]	344	1			T13	1		T216	1		T12	61
valid_sources[0x55]	334	1			T21	5		T30	2		T13	2
valid_sources[0x56]	520	1			T21	20		T13	1		T12	10
valid_sources[0x57]	329	1			T39	2		T21	133		T30	1
valid_sources[0x58]	674	1			T60	1		T13	53		T42	1
valid_sources[0x59]	733	1			T21	2		T201	1		T12	8
valid_sources[0x5a]	773	1			T21	2		T13	333		T191	1
valid_sources[0x5b]	469	1			T199	2		T12	95		T46	5
valid_sources[0x5c]	300	1			T9	1		T21	62		T217	3
valid_sources[0x5d]	562	1			T21	1		T66	1		T46	114
valid_sources[0x5e]	641	1			T217	3		T87	29		T84	3
valid_sources[0x5f]	311	1			T21	90		T11	1		T218	1
valid_sources[0x60]	384	1			T6	7		T13	152		T84	2
valid_sources[0x61]	262	1			T100	1		T84	29		T19	13
valid_sources[0x62]	284	1			T12	108		T19	18		T178	2
valid_sources[0x63]	382	1			T12	88		T84	1		T19	16
valid_sources[0x64]	850	1			T33	1		T13	140		T12	1
valid_sources[0x65]	509	1			T61	1		T217	1		T12	142
valid_sources[0x66]	357	1			T12	10		T193	2		T19	8
valid_sources[0x67]	763	1			T21	50		T13	281		T87	1
valid_sources[0x68]	210	1			T12	2		T155	7		T19	20
valid_sources[0x69]	182	1			T97	1		T21	1		T44	1
valid_sources[0x6a]	279	1			T13	48		T12	1		T46	1
valid_sources[0x6b]	402	1			T60	1		T22	1		T84	3
valid_sources[0x6c]	219	1			T13	4		T205	1		T219	1
valid_sources[0x6d]	418	1			T14	1		T12	1		T76	1
valid_sources[0x6e]	794	1			T13	435		T12	39		T19	21
valid_sources[0x6f]	414	1			T21	8		T13	149		T14	1
valid_sources[0x70]	494	1			T21	43		T204	1		T12	67
valid_sources[0x71]	270	1			T21	1		T12	1		T46	2
valid_sources[0x72]	494	1			T21	56		T12	4		T87	158
valid_sources[0x73]	174	1			T21	1		T19	11		T162	3
valid_sources[0x74]	299	1			T60	1		T220	1		T195	1
valid_sources[0x75]	355	1			T19	26		T190	1		T85	4
valid_sources[0x76]	216	1			T21	3		T176	1		T19	29
valid_sources[0x77]	467	1			T21	1		T217	3		T12	2
valid_sources[0x78]	730	1			T21	94		T13	176		T12	93
valid_sources[0x79]	317	1			T21	20		T13	5		T187	1
valid_sources[0x7a]	346	1			T21	9		T13	5		T46	127
valid_sources[0x7b]	377	1			T33	1		T197	1		T19	28
valid_sources[0x7c]	345	1			T46	1		T75	1		T87	3
valid_sources[0x7d]	564	1			T21	1		T17	1		T75	1
valid_sources[0x7e]	314	1			T8	1		T21	5		T13	92
valid_sources[0x7f]	750	1			T221	1		T19	14		T85	19
valid_sources[0x80]	345	1			T1	1		T28	2		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30385

1

T21

1717

T13

1812

T12

1481

values[0x0]

all_enables

biggest_size

42251

1

T1

4

T2

1

T3

1

values[0x1]

all_enables

biggest_size

42519

1

T1

2

T7

1

T9

4