Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

727939

1

T7

1

T8

4

T9

4

full_word

596804

1

T7

1

T8

3

T9

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1324443	1			T7	2		T8	7		T9	10
auto[TlIntgErrCmd]	96	1			T149	4		T150	6		T139	7
auto[TlIntgErrData]	98	1			T149	7		T150	7		T139	5
auto[TlIntgErrBoth]	106	1			T149	9		T150	7		T139	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

484801

1

T8

3

T9

3

T4

7

auto[1]

839942

1

T7

2

T8

4

T9

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	198934	1			T8	2		T9	1		T4	4
auto[TlIntgErrNone]	partial	auto[1]	528724	1			T7	1		T8	2		T9	3
auto[TlIntgErrNone]	full_word	auto[0]	285718	1			T8	1		T9	2		T4	3
auto[TlIntgErrNone]	full_word	auto[1]	311067	1			T7	1		T8	2		T9	4
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T149	1		T150	1		T139	3
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T149	3		T150	5		T139	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T139	1		T182	1		T183	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T141	1		T181	1		-	-
auto[TlIntgErrData]	partial	auto[0]	50	1			T149	3		T150	5		T139	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T149	4		T150	2		T141	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T183	2		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T139	1		T184	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T149	4		T150	2		T139	8
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T149	4		T150	4		T141	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T185	1		T183	1		T184	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T149	1		T150	1		T185	1