Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	90.48	97.60		100.00	93.75	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	104948961	149156	0	0
late_debug_enable_rd_A	104948961	13876	0	0
late_debug_enable_regwen_rd_A	104948961	13253	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948961	149156	0	0
T10	176462	0	0	0
T12	0	8524	0	0
T13	0	9569	0	0
T16	13671	0	0	0
T18	5524	0	0	0
T19	0	8608	0	0
T21	280034	8761	0	0
T28	586415	0	0	0
T34	66324	0	0	0
T46	0	5893	0	0
T47	0	7857	0	0
T64	108346	0	0	0
T65	80845	0	0	0
T66	269140	0	0	0
T84	0	6125	0	0
T85	0	3044	0	0
T87	0	3937	0	0
T99	0	2947	0	0
T100	3856	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948961	13876	0	0
T19	449209	1425	0	0
T47	0	2795	0	0
T50	3780	0	0	0
T62	10589	0	0	0
T85	0	757	0	0
T86	0	849	0	0
T99	0	1154	0	0
T107	0	10	0	0
T138	0	102	0	0
T139	0	72	0	0
T140	0	114	0	0
T141	0	88	0	0
T142	199032	0	0	0
T143	45997	0	0	0
T144	44284	0	0	0
T145	55547	0	0	0
T146	126713	0	0	0
T147	128564	0	0	0
T148	11847	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104948961	13253	0	0
T19	449209	1265	0	0
T47	0	2387	0	0
T50	3780	0	0	0
T62	10589	0	0	0
T85	0	795	0	0
T86	0	684	0	0
T99	0	1147	0	0
T107	0	9	0	0
T108	0	963	0	0
T138	0	41	0	0
T139	0	83	0	0
T140	0	64	0	0
T142	199032	0	0	0
T143	45997	0	0	0
T144	44284	0	0	0
T145	55547	0	0	0
T146	126713	0	0	0
T147	128564	0	0	0
T148	11847	0	0	0