Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
1 | 1 | Covered | T79 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T79 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7800588 |
7799096 |
0 |
0 |
selKnown1 |
57771522 |
57770030 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7800588 |
7799096 |
0 |
0 |
T1 |
139670 |
139666 |
0 |
0 |
T2 |
17738 |
17734 |
0 |
0 |
T3 |
9086 |
9082 |
0 |
0 |
T4 |
19828 |
19824 |
0 |
0 |
T5 |
2702 |
2698 |
0 |
0 |
T6 |
0 |
10 |
0 |
0 |
T7 |
1822 |
1818 |
0 |
0 |
T8 |
2730 |
2726 |
0 |
0 |
T9 |
20130 |
20126 |
0 |
0 |
T21 |
0 |
15 |
0 |
0 |
T26 |
233644 |
233640 |
0 |
0 |
T28 |
0 |
14 |
0 |
0 |
T29 |
1340 |
1336 |
0 |
0 |
T34 |
0 |
40 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
T48 |
0 |
15 |
0 |
0 |
T65 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
57771522 |
57770030 |
0 |
0 |
T1 |
784105 |
784101 |
0 |
0 |
T2 |
100389 |
100385 |
0 |
0 |
T3 |
131353 |
131349 |
0 |
0 |
T4 |
428920 |
428916 |
0 |
0 |
T5 |
24579 |
24575 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
7348 |
7344 |
0 |
0 |
T8 |
55449 |
55445 |
0 |
0 |
T9 |
275035 |
275031 |
0 |
0 |
T21 |
0 |
10 |
0 |
0 |
T26 |
583716 |
583713 |
0 |
0 |
T28 |
0 |
14 |
0 |
0 |
T29 |
7767 |
7763 |
0 |
0 |
T34 |
0 |
40 |
0 |
0 |
T39 |
0 |
8 |
0 |
0 |
T48 |
0 |
14 |
0 |
0 |
T65 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
1 | 1 | Covered | T79 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T79 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2567970 |
2567707 |
0 |
0 |
selKnown1 |
52539038 |
52538775 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2567970 |
2567707 |
0 |
0 |
T1 |
69829 |
69828 |
0 |
0 |
T2 |
8868 |
8867 |
0 |
0 |
T3 |
4542 |
4541 |
0 |
0 |
T4 |
9908 |
9907 |
0 |
0 |
T5 |
1350 |
1349 |
0 |
0 |
T7 |
910 |
909 |
0 |
0 |
T8 |
1364 |
1363 |
0 |
0 |
T9 |
10058 |
10057 |
0 |
0 |
T26 |
116821 |
116820 |
0 |
0 |
T29 |
669 |
668 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
52539038 |
52538775 |
0 |
0 |
T1 |
714264 |
714263 |
0 |
0 |
T2 |
91519 |
91518 |
0 |
0 |
T3 |
126809 |
126808 |
0 |
0 |
T4 |
419002 |
419001 |
0 |
0 |
T5 |
23227 |
23226 |
0 |
0 |
T7 |
6436 |
6435 |
0 |
0 |
T8 |
54083 |
54082 |
0 |
0 |
T9 |
264965 |
264964 |
0 |
0 |
T26 |
466893 |
466893 |
0 |
0 |
T29 |
7096 |
7095 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
1 | 1 | Covered | T79 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T79 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
820 |
557 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
7 |
6 |
0 |
0 |
T21 |
0 |
7 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T39 |
0 |
9 |
0 |
0 |
T48 |
0 |
7 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
761 |
498 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T39 |
0 |
4 |
0 |
0 |
T48 |
0 |
7 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
1 | 1 | Covered | T79 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T79 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
5230004 |
5229521 |
0 |
0 |
selKnown1 |
5230003 |
5229520 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5230004 |
5229521 |
0 |
0 |
T1 |
69829 |
69828 |
0 |
0 |
T2 |
8868 |
8867 |
0 |
0 |
T3 |
4542 |
4541 |
0 |
0 |
T4 |
9908 |
9907 |
0 |
0 |
T5 |
1350 |
1349 |
0 |
0 |
T7 |
910 |
909 |
0 |
0 |
T8 |
1364 |
1363 |
0 |
0 |
T9 |
10058 |
10057 |
0 |
0 |
T26 |
116821 |
116820 |
0 |
0 |
T29 |
669 |
668 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
5230003 |
5229520 |
0 |
0 |
T1 |
69829 |
69828 |
0 |
0 |
T2 |
8868 |
8867 |
0 |
0 |
T3 |
4542 |
4541 |
0 |
0 |
T4 |
9908 |
9907 |
0 |
0 |
T5 |
1350 |
1349 |
0 |
0 |
T7 |
910 |
909 |
0 |
0 |
T8 |
1364 |
1363 |
0 |
0 |
T9 |
10058 |
10057 |
0 |
0 |
T26 |
116821 |
116820 |
0 |
0 |
T29 |
669 |
668 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T79 |
1 | 1 | Covered | T79 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T79 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1794 |
1311 |
0 |
0 |
selKnown1 |
1720 |
1237 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1794 |
1311 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
7 |
6 |
0 |
0 |
T21 |
0 |
8 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T39 |
0 |
9 |
0 |
0 |
T48 |
0 |
8 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1720 |
1237 |
0 |
0 |
T1 |
6 |
5 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
1 |
0 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
0 |
3 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T26 |
1 |
0 |
0 |
0 |
T28 |
0 |
7 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T39 |
0 |
4 |
0 |
0 |
T48 |
0 |
7 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |