SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.36 | 100.00 | 90.48 | 97.60 | 100.00 | 93.75 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 52539038 | 52475756 | 0 | 0 |
gen_no_flops.OutputDelay_A | 52539038 | 52475756 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52539038 | 52475756 | 0 | 0 |
T1 | 714264 | 713931 | 0 | 0 |
T2 | 91519 | 91469 | 0 | 0 |
T3 | 126809 | 126755 | 0 | 0 |
T4 | 419002 | 418661 | 0 | 0 |
T5 | 23227 | 23171 | 0 | 0 |
T7 | 6436 | 6365 | 0 | 0 |
T8 | 54083 | 54008 | 0 | 0 |
T9 | 264965 | 264561 | 0 | 0 |
T26 | 466893 | 466887 | 0 | 0 |
T29 | 7096 | 7016 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 52539038 | 52475756 | 0 | 0 |
T1 | 714264 | 713931 | 0 | 0 |
T2 | 91519 | 91469 | 0 | 0 |
T3 | 126809 | 126755 | 0 | 0 |
T4 | 419002 | 418661 | 0 | 0 |
T5 | 23227 | 23171 | 0 | 0 |
T7 | 6436 | 6365 | 0 | 0 |
T8 | 54083 | 54008 | 0 | 0 |
T9 | 264965 | 264561 | 0 | 0 |
T26 | 466893 | 466887 | 0 | 0 |
T29 | 7096 | 7016 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |