Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

649439

1

T2

1

T3

2

T12

3

full_word

650135

1

T6

2

T45

1

T13

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1299234	1			T2	1		T3	2		T6	2
auto[TlIntgErrCmd]	111	1			T167	3		T168	10		T169	2
auto[TlIntgErrData]	107	1			T167	3		T168	7		T169	5
auto[TlIntgErrBoth]	122	1			T167	4		T168	3		T169	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

555778

1

T12

1

T44

3

T14

1

auto[1]

743796

1

T2

1

T3

2

T6

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	231075	1			T12	1		T44	2		T14	1
auto[TlIntgErrNone]	partial	auto[1]	418056	1			T2	1		T3	2		T12	2
auto[TlIntgErrNone]	full_word	auto[0]	324558	1			T44	1		T62	5		T59	6
auto[TlIntgErrNone]	full_word	auto[1]	325545	1			T6	2		T45	1		T13	1
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T167	2		T168	3		T169	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T168	7		T200	7		T197	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T167	1		T197	1		T204	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T169	1		T197	1		T201	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T167	1		T168	4		T169	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T167	2		T168	2		T169	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T200	1		T205	2		T204	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T168	1		T205	1		T206	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T167	2		T169	3		T200	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T167	2		T168	2		T169	9
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T168	1		T169	1		T201	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T201	1		T198	1		T199	2