Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	90.48	97.60		100.00	93.75	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	138244697	121993	0	0
late_debug_enable_rd_A	138244697	6970	0	0
late_debug_enable_regwen_rd_A	138244697	6067	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138244697	121993	0	0
T26	0	5942	0	0
T29	42921	0	0	0
T32	0	3932	0	0
T34	0	6227	0	0
T55	0	8320	0	0
T61	67409	1436	0	0
T69	0	411	0	0
T70	0	2923	0	0
T71	0	2572	0	0
T73	31676	0	0	0
T108	0	4783	0	0
T114	0	311	0	0
T115	235924	0	0	0
T116	102870	0	0	0
T117	544893	0	0	0
T118	2422	0	0	0
T119	113116	0	0	0
T120	132082	0	0	0
T121	692200	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138244697	6970	0	0
T26	0	2441	0	0
T29	42921	0	0	0
T61	67409	338	0	0
T69	0	225	0	0
T70	0	687	0	0
T73	31676	0	0	0
T115	235924	0	0	0
T116	102870	0	0	0
T117	544893	0	0	0
T118	2422	0	0	0
T119	113116	0	0	0
T120	132082	0	0	0
T121	692200	0	0	0
T126	0	5	0	0
T127	0	79	0	0
T130	0	50	0	0
T132	0	1	0	0
T166	0	7	0	0
T167	0	33	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138244697	6067	0	0
T26	0	2080	0	0
T29	42921	0	0	0
T61	67409	210	0	0
T69	0	169	0	0
T70	0	638	0	0
T73	31676	0	0	0
T115	235924	0	0	0
T116	102870	0	0	0
T117	544893	0	0	0
T118	2422	0	0	0
T119	113116	0	0	0
T120	132082	0	0	0
T121	692200	0	0	0
T126	0	1	0	0
T127	0	43	0	0
T129	0	7	0	0
T130	0	22	0	0
T166	0	12	0	0
T167	0	55	0	0