Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33			83.33

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_alert_tx[0].u_prim_alert_sender	83.33			83.33

---

Module Instance : tb.dut.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33			83.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33			83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	90.48	97.60		100.00	93.75	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	10	83.33
Total Bits	24	20	83.33
Total Bits 0->1	12	10	83.33
Total Bits 1->0	12	10	83.33

Ports	12	10	83.33
Port Bits	24	20	83.33
Port Bits 0->1	12	10	83.33
Port Bits 1->0	12	10	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T46,T15,T47	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	INPUT
alert_req_i	Yes	Yes	T46,T47,T51	Yes	T46,T47,T51	INPUT
alert_ack_o	Yes	Yes	T46,T47,T51	Yes	T46,T47,T51	OUTPUT
alert_state_o	Yes	Yes	T46,T47,T51	Yes	T46,T47,T51	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T46,T48,T47	Yes	T46,T48,T47	INPUT
alert_rx_i.ping_n	No	No		No		INPUT
alert_rx_i.ping_p	No	No		No		INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T46,T48,T47	Yes	T46,T48,T47	OUTPUT