Line Coverage for Module :
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
24
25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i);
Tests: T1 T2 T3
26
27 prim_secded_inv_64_57_enc u_rsp_gen (
28 .data_i(D2HRspMaxWidth'(rsp)),
29 .data_o({rsp_intg, unused_payload})
30 );
31 end else begin : gen_passthrough_rsp_intg
32 assign rsp_intg = tl_i.d_user.rsp_intg;
33 end
34
35 logic [DataIntgWidth-1:0] data_intg;
36 if (EnableDataIntgGen) begin : gen_data_intg
37 logic [DataMaxWidth-1:0] unused_data;
38 tlul_data_integ_enc u_tlul_data_integ_enc (
39 .data_i(DataMaxWidth'(tl_i.d_data)),
40 .data_intg_o({data_intg, unused_data})
41 );
42 end else begin : gen_passthrough_data_intg
43 assign data_intg = tl_i.d_user.data_intg;
44 end
45
46 always_comb begin
47 1/1 tl_o = tl_i;
Tests: T1 T2 T3
48 1/1 tl_o.d_user.rsp_intg = rsp_intg;
Tests: T1 T2 T3
49 1/1 tl_o.d_user.data_intg = data_intg;
Tests: T1 T2 T3
50 end
51
52 logic unused_tl;
53 1/1 assign unused_tl = ^tl_i;
Tests: T1 T2 T3
Line Coverage for Module :
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 4 | 66.67 |
CONT_ASSIGN | 32 | 1 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
31 end else begin : gen_passthrough_rsp_intg
32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg;
33 end
34
35 logic [DataIntgWidth-1:0] data_intg;
36 if (EnableDataIntgGen) begin : gen_data_intg
37 logic [DataMaxWidth-1:0] unused_data;
38 tlul_data_integ_enc u_tlul_data_integ_enc (
39 .data_i(DataMaxWidth'(tl_i.d_data)),
40 .data_intg_o({data_intg, unused_data})
41 );
42 end else begin : gen_passthrough_data_intg
43 0/1 ==> assign data_intg = tl_i.d_user.data_intg;
44 end
45
46 always_comb begin
47 1/1 tl_o = tl_i;
Tests: T1 T2 T3
48 1/1 tl_o.d_user.rsp_intg = rsp_intg;
Tests: T1 T2 T3
49 1/1 tl_o.d_user.data_intg = data_intg;
Tests: T1 T2 T3
50 end
51
52 logic unused_tl;
53 1/1 assign unused_tl = ^tl_i;
Tests: T1 T2 T3
Assert Coverage for Module :
tlul_rsp_intg_gen
Assertion Details
DataWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1750 |
1750 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
5 |
5 |
0 |
0 |
T3 |
5 |
5 |
0 |
0 |
T4 |
5 |
5 |
0 |
0 |
T5 |
5 |
5 |
0 |
0 |
T6 |
5 |
5 |
0 |
0 |
T12 |
5 |
5 |
0 |
0 |
T13 |
5 |
5 |
0 |
0 |
T18 |
5 |
5 |
0 |
0 |
T45 |
5 |
5 |
0 |
0 |
PayLoadWidthCheck
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1750 |
1750 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
5 |
5 |
0 |
0 |
T3 |
5 |
5 |
0 |
0 |
T4 |
5 |
5 |
0 |
0 |
T5 |
5 |
5 |
0 |
0 |
T6 |
5 |
5 |
0 |
0 |
T12 |
5 |
5 |
0 |
0 |
T13 |
5 |
5 |
0 |
0 |
T18 |
5 |
5 |
0 |
0 |
T45 |
5 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 4 | 66.67 |
CONT_ASSIGN | 32 | 1 | 0 | 0.00 |
CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
31 end else begin : gen_passthrough_rsp_intg
32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg;
33 end
34
35 logic [DataIntgWidth-1:0] data_intg;
36 if (EnableDataIntgGen) begin : gen_data_intg
37 logic [DataMaxWidth-1:0] unused_data;
38 tlul_data_integ_enc u_tlul_data_integ_enc (
39 .data_i(DataMaxWidth'(tl_i.d_data)),
40 .data_intg_o({data_intg, unused_data})
41 );
42 end else begin : gen_passthrough_data_intg
43 0/1 ==> assign data_intg = tl_i.d_user.data_intg;
44 end
45
46 always_comb begin
47 1/1 tl_o = tl_i;
Tests: T1 T2 T3
48 1/1 tl_o.d_user.rsp_intg = rsp_intg;
Tests: T1 T2 T3
49 1/1 tl_o.d_user.data_intg = data_intg;
Tests: T1 T2 T3
50 end
51
52 logic unused_tl;
53 1/1 assign unused_tl = ^tl_i;
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_reg_regs.u_reg_if.u_rsp_intg_gen
Assertion Details
DataWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482 |
482 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
PayLoadWidthCheck
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482 |
482 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_rsp_intg_gen
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
24
25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i);
Tests: T1 T2 T3
26
27 prim_secded_inv_64_57_enc u_rsp_gen (
28 .data_i(D2HRspMaxWidth'(rsp)),
29 .data_o({rsp_intg, unused_payload})
30 );
31 end else begin : gen_passthrough_rsp_intg
32 assign rsp_intg = tl_i.d_user.rsp_intg;
33 end
34
35 logic [DataIntgWidth-1:0] data_intg;
36 if (EnableDataIntgGen) begin : gen_data_intg
37 logic [DataMaxWidth-1:0] unused_data;
38 tlul_data_integ_enc u_tlul_data_integ_enc (
39 .data_i(DataMaxWidth'(tl_i.d_data)),
40 .data_intg_o({data_intg, unused_data})
41 );
42 end else begin : gen_passthrough_data_intg
43 assign data_intg = tl_i.d_user.data_intg;
44 end
45
46 always_comb begin
47 1/1 tl_o = tl_i;
Tests: T1 T2 T3
48 1/1 tl_o.d_user.rsp_intg = rsp_intg;
Tests: T1 T2 T3
49 1/1 tl_o.d_user.data_intg = data_intg;
Tests: T1 T2 T3
50 end
51
52 logic unused_tl;
53 1/1 assign unused_tl = ^tl_i;
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_reg_regs.u_rsp_intg_gen
Assertion Details
DataWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482 |
482 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
PayLoadWidthCheck
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482 |
482 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
24
25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i);
Tests: T1 T2 T3
26
27 prim_secded_inv_64_57_enc u_rsp_gen (
28 .data_i(D2HRspMaxWidth'(rsp)),
29 .data_o({rsp_intg, unused_payload})
30 );
31 end else begin : gen_passthrough_rsp_intg
32 assign rsp_intg = tl_i.d_user.rsp_intg;
33 end
34
35 logic [DataIntgWidth-1:0] data_intg;
36 if (EnableDataIntgGen) begin : gen_data_intg
37 logic [DataMaxWidth-1:0] unused_data;
38 tlul_data_integ_enc u_tlul_data_integ_enc (
39 .data_i(DataMaxWidth'(tl_i.d_data)),
40 .data_intg_o({data_intg, unused_data})
41 );
42 end else begin : gen_passthrough_data_intg
43 assign data_intg = tl_i.d_user.data_intg;
44 end
45
46 always_comb begin
47 1/1 tl_o = tl_i;
Tests: T1 T2 T3
48 1/1 tl_o.d_user.rsp_intg = rsp_intg;
Tests: T1 T2 T3
49 1/1 tl_o.d_user.data_intg = data_intg;
Tests: T1 T2 T3
50 end
51
52 logic unused_tl;
53 1/1 assign unused_tl = ^tl_i;
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp.u_intg_gen
Assertion Details
DataWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
PayLoadWidthCheck
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
24
25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i);
Tests: T1 T2 T3
26
27 prim_secded_inv_64_57_enc u_rsp_gen (
28 .data_i(D2HRspMaxWidth'(rsp)),
29 .data_o({rsp_intg, unused_payload})
30 );
31 end else begin : gen_passthrough_rsp_intg
32 assign rsp_intg = tl_i.d_user.rsp_intg;
33 end
34
35 logic [DataIntgWidth-1:0] data_intg;
36 if (EnableDataIntgGen) begin : gen_data_intg
37 logic [DataMaxWidth-1:0] unused_data;
38 tlul_data_integ_enc u_tlul_data_integ_enc (
39 .data_i(DataMaxWidth'(tl_i.d_data)),
40 .data_intg_o({data_intg, unused_data})
41 );
42 end else begin : gen_passthrough_data_intg
43 assign data_intg = tl_i.d_user.data_intg;
44 end
45
46 always_comb begin
47 1/1 tl_o = tl_i;
Tests: T1 T2 T3
48 1/1 tl_o.d_user.rsp_intg = rsp_intg;
Tests: T1 T2 T3
49 1/1 tl_o.d_user.data_intg = data_intg;
Tests: T1 T2 T3
50 end
51
52 logic unused_tl;
53 1/1 assign unused_tl = ^tl_i;
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp.u_intg_gen
Assertion Details
DataWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
PayLoadWidthCheck
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
ALWAYS | 47 | 3 | 3 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
24
25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i);
Tests: T1 T2 T3
26
27 prim_secded_inv_64_57_enc u_rsp_gen (
28 .data_i(D2HRspMaxWidth'(rsp)),
29 .data_o({rsp_intg, unused_payload})
30 );
31 end else begin : gen_passthrough_rsp_intg
32 assign rsp_intg = tl_i.d_user.rsp_intg;
33 end
34
35 logic [DataIntgWidth-1:0] data_intg;
36 if (EnableDataIntgGen) begin : gen_data_intg
37 logic [DataMaxWidth-1:0] unused_data;
38 tlul_data_integ_enc u_tlul_data_integ_enc (
39 .data_i(DataMaxWidth'(tl_i.d_data)),
40 .data_intg_o({data_intg, unused_data})
41 );
42 end else begin : gen_passthrough_data_intg
43 assign data_intg = tl_i.d_user.data_intg;
44 end
45
46 always_comb begin
47 1/1 tl_o = tl_i;
Tests: T1 T2 T3
48 1/1 tl_o.d_user.rsp_intg = rsp_intg;
Tests: T1 T2 T3
49 1/1 tl_o.d_user.data_intg = data_intg;
Tests: T1 T2 T3
50 end
51
52 logic unused_tl;
53 1/1 assign unused_tl = ^tl_i;
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.i_tlul_adapter_reg.u_rsp_intg_gen
Assertion Details
DataWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |
PayLoadWidthCheck
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T45 |
1 |
1 |
0 |
0 |