Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	100.00	100.00					100.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	90.48	97.60		100.00	93.75	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

28                        logic late_debug_enable;
29         1/1            assign late_debug_enable =
           Tests:       T1 T2 T3 
30                          mubi8_test_true_strict(otp_dis_rv_dm_late_debug_i) ||
31                          mubi32_test_true_strict(prim_mubi_pkg::mubi32_t'(regs_reg2hw.late_debug_enable));
32                      
33                        // Should debug be enabled? If we're using late_debug_enable, this is governed by
34                        // lc_hw_debug_en_i. If not, it comes from lc_dft_en_i.
35                        logic debug_enabled;
36         1/1            assign debug_enabled = lc_tx_test_true_strict(late_debug_enable ? lc_hw_debug_en_i : lc_dft_en_i);
           Tests:       T4 T45 T18 

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	63930689	63879583	0	0
MemTLResponseWithoutDebugIsError_A	63721841	63670735	0	0
NdmResetAckNeedsDebug_A	63931491	63880385	0	0
SbaTLRequestNeedsDebug_A	63721841	63670735	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63930689	63879583	0	0
T1	15821	15759	0	0
T2	9812	9730	0	0
T3	18723	18651	0	0
T4	31326	31250	0	0
T5	43976	43913	0	0
T6	1659	1577	0	0
T12	29987	29916	0	0
T13	34292	34220	0	0
T18	58244	58175	0	0
T45	24793	24725	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63721841	63670735	0	0
T1	15821	15759	0	0
T2	9812	9730	0	0
T3	18723	18651	0	0
T4	31326	31250	0	0
T5	43976	43913	0	0
T6	1659	1577	0	0
T12	29987	29916	0	0
T13	34292	34220	0	0
T18	58244	58175	0	0
T45	24793	24725	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63931491	63880385	0	0
T1	15821	15759	0	0
T2	9812	9730	0	0
T3	18723	18651	0	0
T4	31326	31250	0	0
T5	43976	43913	0	0
T6	1659	1577	0	0
T12	29987	29916	0	0
T13	34292	34220	0	0
T18	58244	58175	0	0
T45	24793	24725	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63721841	63670735	0	0
T1	15821	15759	0	0
T2	9812	9730	0	0
T3	18723	18651	0	0
T4	31326	31250	0	0
T5	43976	43913	0	0
T6	1659	1577	0	0
T12	29987	29916	0	0
T13	34292	34220	0	0
T18	58244	58175	0	0
T45	24793	24725	0	0