Line Coverage for Module :
dmi_jtag_tap
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 96 | 96 | 100.00 |
| ALWAYS | 79 | 11 | 11 | 100.00 |
| ALWAYS | 105 | 5 | 5 | 100.00 |
| ALWAYS | 127 | 15 | 15 | 100.00 |
| ALWAYS | 151 | 10 | 10 | 100.00 |
| ALWAYS | 172 | 6 | 6 | 100.00 |
| ALWAYS | 201 | 5 | 5 | 100.00 |
| ALWAYS | 215 | 31 | 31 | 100.00 |
| ALWAYS | 302 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 315 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 318 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 319 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
78 always_comb begin : p_jtag
79 1/1 jtag_ir_shift_d = jtag_ir_shift_q;
Tests: T1 T2 T3
80 1/1 jtag_ir_d = jtag_ir_q;
Tests: T1 T2 T3
81
82 // IR shift register
83 1/1 if (shift_ir) begin
Tests: T1 T2 T3
84 1/1 jtag_ir_shift_d = {td_i, jtag_ir_shift_q[IrLength-1:1]};
Tests: T1 T2 T3
85 end
MISSING_ELSE
86
87 // capture IR register
88 1/1 if (capture_ir) begin
Tests: T1 T2 T3
89 1/1 jtag_ir_shift_d = IrLength'(4'b0101);
Tests: T1 T2 T3
90 end
MISSING_ELSE
91
92 // update IR register
93 1/1 if (update_ir) begin
Tests: T1 T2 T3
94 1/1 jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
Tests: T1 T2 T3
95 end
MISSING_ELSE
96
97 1/1 if (test_logic_reset) begin
Tests: T1 T2 T3
98 // Bring all TAP state to the initial value.
99 1/1 jtag_ir_shift_d = '0;
Tests: T1 T2 T3
100 1/1 jtag_ir_d = IDCODE;
Tests: T1 T2 T3
101 end
MISSING_ELSE
102 end
103
104 always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg
105 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
106 1/1 jtag_ir_shift_q <= '0;
Tests: T1 T2 T3
107 1/1 jtag_ir_q <= IDCODE;
Tests: T1 T2 T3
108 end else begin
109 1/1 jtag_ir_shift_q <= jtag_ir_shift_d;
Tests: T1 T2 T3
110 1/1 jtag_ir_q <= jtag_ir_d;
Tests: T1 T2 T3
111 end
112 end
113
114 // ----------------
115 // TAP DR Regs
116 // ----------------
117 // - Bypass
118 // - IDCODE
119 // - DTM CS
120 logic [31:0] idcode_d, idcode_q;
121 logic idcode_select;
122 logic bypass_select;
123
124 logic bypass_d, bypass_q; // this is a 1-bit register
125
126 always_comb begin
127 1/1 idcode_d = idcode_q;
Tests: T1 T2 T3
128 1/1 bypass_d = bypass_q;
Tests: T1 T2 T3
129
130 1/1 if (capture_dr) begin
Tests: T1 T2 T3
131 2/2 if (idcode_select) idcode_d = IdcodeValue;
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
132 2/2 if (bypass_select) bypass_d = 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
133 end
MISSING_ELSE
134
135 1/1 if (shift_dr) begin
Tests: T1 T2 T3
136 2/2 if (idcode_select) idcode_d = {td_i, 31'(idcode_q >> 1)};
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
137 2/2 if (bypass_select) bypass_d = td_i;
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
138 end
MISSING_ELSE
139
140 1/1 if (test_logic_reset) begin
Tests: T1 T2 T3
141 // Bring all TAP state to the initial value.
142 1/1 idcode_d = IdcodeValue;
Tests: T1 T2 T3
143 1/1 bypass_d = 1'b0;
Tests: T1 T2 T3
144 end
MISSING_ELSE
145 end
146
147 // ----------------
148 // Data reg select
149 // ----------------
150 always_comb begin : p_data_reg_sel
151 1/1 dmi_select_o = 1'b0;
Tests: T1 T2 T3
152 1/1 dtmcs_select_o = 1'b0;
Tests: T1 T2 T3
153 1/1 idcode_select = 1'b0;
Tests: T1 T2 T3
154 1/1 bypass_select = 1'b0;
Tests: T1 T2 T3
155 1/1 unique case (jtag_ir_q)
Tests: T1 T2 T3
156 1/1 BYPASS0: bypass_select = 1'b1;
Tests: T89 T82 T96
157 1/1 IDCODE: idcode_select = 1'b1;
Tests: T1 T2 T3
158 1/1 DTMCSR: dtmcs_select_o = 1'b1;
Tests: T3 T13 T36
159 1/1 DMIACCESS: dmi_select_o = 1'b1;
Tests: T1 T2 T3
160 1/1 BYPASS1: bypass_select = 1'b1;
Tests: T96 T97 T98
161 default: bypass_select = 1'b1;
162 endcase
163 end
164
165 // ----------------
166 // Output select
167 // ----------------
168 logic tdo_mux;
169
170 always_comb begin : p_out_sel
171 // we are shifting out the IR register
172 1/1 if (shift_ir) begin
Tests: T1 T2 T3
173 1/1 tdo_mux = jtag_ir_shift_q[0];
Tests: T1 T2 T3
174 // here we are shifting the DR register
175 end else begin
176 1/1 unique case (jtag_ir_q)
Tests: T1 T2 T3
177 1/1 IDCODE: tdo_mux = idcode_q[0]; // Reading ID code
Tests: T1 T2 T3
178 1/1 DTMCSR: tdo_mux = dtmcs_tdo_i; // Read from DTMCS TDO
Tests: T3 T13 T36
179 1/1 DMIACCESS: tdo_mux = dmi_tdo_i; // Read from DMI TDO
Tests: T1 T2 T3
180 default: tdo_mux = bypass_q; // BYPASS instruction
181 endcase
182 end
183 end
184
185 // ----------------
186 // DFT
187 // ----------------
188 logic tck_n;
189
190 prim_clock_inv #(
191 .HasScanMode(1'b1),
192 .NoFpgaBufG(1'b1)
193 ) i_tck_inv (
194 .clk_i ( tck_i ),
195 .clk_no ( tck_n ),
196 .scanmode_i ( testmode_i )
197 );
198
199 // TDO changes state at negative edge of TCK
200 always_ff @(posedge tck_n, negedge trst_ni) begin : p_tdo_regs
201 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
202 1/1 td_o <= 1'b0;
Tests: T1 T2 T3
203 1/1 tdo_oe_o <= 1'b0;
Tests: T1 T2 T3
204 end else begin
205 1/1 td_o <= tdo_mux;
Tests: T1 T2 T3
206 1/1 tdo_oe_o <= (shift_ir | shift_dr);
Tests: T1 T2 T3
207 end
208 end
209 // ----------------
210 // TAP FSM
211 // ----------------
212 // Determination of next state; purely combinatorial
213 always_comb begin : p_tap_fsm
214
215 1/1 test_logic_reset = 1'b0;
Tests: T1 T2 T3
216
217 1/1 capture_dr = 1'b0;
Tests: T1 T2 T3
218 1/1 shift_dr = 1'b0;
Tests: T1 T2 T3
219 1/1 update_dr = 1'b0;
Tests: T1 T2 T3
220
221 1/1 capture_ir = 1'b0;
Tests: T1 T2 T3
222 1/1 shift_ir = 1'b0;
Tests: T1 T2 T3
223 // pause_ir = 1'b0; unused
224 1/1 update_ir = 1'b0;
Tests: T1 T2 T3
225
226 1/1 unique case (tap_state_q)
Tests: T1 T2 T3
227 TestLogicReset: begin
228 1/1 tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
Tests: T1 T2 T3
229 1/1 test_logic_reset = 1'b1;
Tests: T1 T2 T3
230 end
231 RunTestIdle: begin
232 1/1 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
Tests: T1 T2 T3
233 end
234 // DR Path
235 SelectDrScan: begin
236 1/1 tap_state_d = (tms_i) ? SelectIrScan : CaptureDr;
Tests: T1 T2 T3
237 end
238 CaptureDr: begin
239 1/1 capture_dr = 1'b1;
Tests: T1 T2 T3
240 1/1 tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
Tests: T1 T2 T3
241 end
242 ShiftDr: begin
243 1/1 shift_dr = 1'b1;
Tests: T1 T2 T3
244 1/1 tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
Tests: T1 T2 T3
245 end
246 Exit1Dr: begin
247 1/1 tap_state_d = (tms_i) ? UpdateDr : PauseDr;
Tests: T1 T2 T3
248 end
249 PauseDr: begin
250 1/1 tap_state_d = (tms_i) ? Exit2Dr : PauseDr;
Tests: T1 T2 T3
251 end
252 Exit2Dr: begin
253 1/1 tap_state_d = (tms_i) ? UpdateDr : ShiftDr;
Tests: T1 T2 T3
254 end
255 UpdateDr: begin
256 1/1 update_dr = 1'b1;
Tests: T1 T2 T3
257 1/1 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
Tests: T1 T2 T3
258 end
259 // IR Path
260 SelectIrScan: begin
261 1/1 tap_state_d = (tms_i) ? TestLogicReset : CaptureIr;
Tests: T1 T2 T3
262 end
263 // In this controller state, the shift register bank in the
264 // Instruction Register parallel loads a pattern of fixed values on
265 // the rising edge of TCK. The last two significant bits must always
266 // be "01".
267 CaptureIr: begin
268 1/1 capture_ir = 1'b1;
Tests: T1 T2 T3
269 1/1 tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
Tests: T1 T2 T3
270 end
271 // In this controller state, the instruction register gets connected
272 // between TDI and TDO, and the captured pattern gets shifted on
273 // each rising edge of TCK. The instruction available on the TDI
274 // pin is also shifted in to the instruction register.
275 ShiftIr: begin
276 1/1 shift_ir = 1'b1;
Tests: T1 T2 T3
277 1/1 tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
Tests: T1 T2 T3
278 end
279 Exit1Ir: begin
280 1/1 tap_state_d = (tms_i) ? UpdateIr : PauseIr;
Tests: T1 T2 T3
281 end
282 PauseIr: begin
283 // pause_ir = 1'b1; // unused
284 1/1 tap_state_d = (tms_i) ? Exit2Ir : PauseIr;
Tests: T1 T2 T3
285 end
286 Exit2Ir: begin
287 1/1 tap_state_d = (tms_i) ? UpdateIr : ShiftIr;
Tests: T1 T2 T3
288 end
289 // In this controller state, the instruction in the instruction
290 // shift register is latched to the latch bank of the Instruction
291 // Register on every falling edge of TCK. This instruction becomes
292 // the current instruction once it is latched.
293 UpdateIr: begin
294 1/1 update_ir = 1'b1;
Tests: T1 T2 T3
295 1/1 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
Tests: T1 T2 T3
296 end
297 default: ; // can't actually happen since case is full
298 endcase
299 end
300
301 always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
302 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
303 1/1 tap_state_q <= TestLogicReset;
Tests: T1 T2 T3
304 1/1 idcode_q <= IdcodeValue;
Tests: T1 T2 T3
305 1/1 bypass_q <= 1'b0;
Tests: T1 T2 T3
306 end else begin
307 1/1 tap_state_q <= tap_state_d;
Tests: T1 T2 T3
308 1/1 idcode_q <= idcode_d;
Tests: T1 T2 T3
309 1/1 bypass_q <= bypass_d;
Tests: T1 T2 T3
310 end
311 end
312
313 // Pass through JTAG signals to debug custom DR logic.
314 // In case of a single TAP those are just feed-through.
315 1/1 assign tck_o = tck_i;
Tests: T1 T2 T3
316 1/1 assign tdi_o = td_i;
Tests: T1 T2 T3
317 1/1 assign update_o = update_dr;
Tests: T1 T2 T3
318 1/1 assign shift_o = shift_dr;
Tests: T1 T2 T3
319 1/1 assign capture_o = capture_dr;
Tests: T1 T2 T3
320 1/1 assign dmi_clear_o = test_logic_reset;
Tests: T1 T2 T3
Cond Coverage for Module :
dmi_jtag_tap
| Total | Covered | Percent |
|---|
| Conditions | 35 | 35 | 100.00 |
| Logical | 35 | 35 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 206
EXPRESSION (shift_ir | shift_dr)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 228
EXPRESSION (tms_i ? TestLogicReset : RunTestIdle)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T89,T82 |
LINE 232
EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (tms_i ? SelectIrScan : CaptureDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 240
EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T82,T99,T100 |
LINE 244
EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (tms_i ? UpdateDr : PauseDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 250
EXPRESSION (tms_i ? Exit2Dr : PauseDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 253
EXPRESSION (tms_i ? UpdateDr : ShiftDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 257
EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 261
EXPRESSION (tms_i ? TestLogicReset : CaptureIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 269
EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T64,T15,T82 |
LINE 277
EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 280
EXPRESSION (tms_i ? UpdateIr : PauseIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 284
EXPRESSION (tms_i ? Exit2Ir : PauseIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T12 |
LINE 287
EXPRESSION (tms_i ? UpdateIr : ShiftIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T12 |
LINE 295
EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Module :
dmi_jtag_tap
Summary for FSM :: tap_state_q
| Total | Covered | Percent | |
| States |
16 |
16 |
100.00 |
(Not included in score) |
| Transitions |
40 |
36 |
90.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: tap_state_q
| states | Line No. | Covered | Tests |
| CaptureDr |
236 |
Covered |
T1,T2,T3 |
| CaptureIr |
261 |
Covered |
T1,T2,T3 |
| Exit1Dr |
240 |
Covered |
T1,T2,T3 |
| Exit1Ir |
269 |
Covered |
T1,T2,T3 |
| Exit2Dr |
250 |
Covered |
T1,T2,T3 |
| Exit2Ir |
284 |
Covered |
T1,T6,T12 |
| PauseDr |
247 |
Covered |
T1,T2,T3 |
| PauseIr |
280 |
Covered |
T1,T6,T12 |
| RunTestIdle |
228 |
Covered |
T1,T2,T3 |
| SelectDrScan |
232 |
Covered |
T1,T2,T3 |
| SelectIrScan |
236 |
Covered |
T1,T2,T3 |
| ShiftDr |
240 |
Covered |
T1,T2,T3 |
| ShiftIr |
269 |
Covered |
T1,T2,T3 |
| TestLogicReset |
303 |
Covered |
T1,T2,T3 |
| UpdateDr |
247 |
Covered |
T1,T2,T3 |
| UpdateIr |
280 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| CaptureDr->Exit1Dr |
240 |
Covered |
T82,T99,T100 |
| CaptureDr->ShiftDr |
240 |
Covered |
T1,T2,T3 |
| CaptureDr->TestLogicReset |
303 |
Covered |
T99 |
| CaptureIr->Exit1Ir |
269 |
Covered |
T64,T15,T82 |
| CaptureIr->ShiftIr |
269 |
Covered |
T1,T2,T3 |
| CaptureIr->TestLogicReset |
303 |
Covered |
T101,T102,T103 |
| Exit1Dr->PauseDr |
247 |
Covered |
T1,T2,T3 |
| Exit1Dr->TestLogicReset |
303 |
Not Covered |
|
| Exit1Dr->UpdateDr |
247 |
Covered |
T1,T2,T3 |
| Exit1Ir->PauseIr |
280 |
Covered |
T1,T6,T12 |
| Exit1Ir->TestLogicReset |
303 |
Covered |
T103,T104,T105 |
| Exit1Ir->UpdateIr |
280 |
Covered |
T1,T2,T3 |
| Exit2Dr->ShiftDr |
253 |
Covered |
T1,T2,T3 |
| Exit2Dr->TestLogicReset |
303 |
Covered |
T106 |
| Exit2Dr->UpdateDr |
253 |
Covered |
T1,T2,T12 |
| Exit2Ir->ShiftIr |
287 |
Covered |
T1,T6,T12 |
| Exit2Ir->TestLogicReset |
303 |
Not Covered |
|
| Exit2Ir->UpdateIr |
287 |
Covered |
T12,T8,T27 |
| PauseDr->Exit2Dr |
250 |
Covered |
T1,T2,T3 |
| PauseDr->TestLogicReset |
303 |
Covered |
T107,T101,T106 |
| PauseIr->Exit2Ir |
284 |
Covered |
T1,T6,T12 |
| PauseIr->TestLogicReset |
303 |
Covered |
T108,T109,T101 |
| RunTestIdle->SelectDrScan |
232 |
Covered |
T1,T2,T3 |
| RunTestIdle->TestLogicReset |
303 |
Covered |
T7,T46,T24 |
| SelectDrScan->CaptureDr |
236 |
Covered |
T1,T2,T3 |
| SelectDrScan->SelectIrScan |
236 |
Covered |
T1,T2,T3 |
| SelectDrScan->TestLogicReset |
303 |
Covered |
T70,T106,T105 |
| SelectIrScan->CaptureIr |
261 |
Covered |
T1,T2,T3 |
| SelectIrScan->TestLogicReset |
303 |
Covered |
T89,T82,T34 |
| ShiftDr->Exit1Dr |
244 |
Covered |
T1,T2,T3 |
| ShiftDr->TestLogicReset |
303 |
Covered |
T61,T69,T70 |
| ShiftIr->Exit1Ir |
277 |
Covered |
T1,T2,T3 |
| ShiftIr->TestLogicReset |
303 |
Covered |
T61,T108,T101 |
| TestLogicReset->RunTestIdle |
228 |
Covered |
T1,T2,T3 |
| UpdateDr->RunTestIdle |
257 |
Covered |
T1,T2,T3 |
| UpdateDr->SelectDrScan |
257 |
Not Covered |
|
| UpdateDr->TestLogicReset |
303 |
Covered |
T82,T71,T26 |
| UpdateIr->RunTestIdle |
295 |
Covered |
T1,T2,T3 |
| UpdateIr->SelectDrScan |
295 |
Not Covered |
|
| UpdateIr->TestLogicReset |
303 |
Covered |
T110,T100,T111 |
Branch Coverage for Module :
dmi_jtag_tap
| Line No. | Total | Covered | Percent |
| Branches |
|
70 |
69 |
98.57 |
| IF |
83 |
2 |
2 |
100.00 |
| IF |
88 |
2 |
2 |
100.00 |
| IF |
93 |
2 |
2 |
100.00 |
| IF |
97 |
2 |
2 |
100.00 |
| IF |
105 |
2 |
2 |
100.00 |
| IF |
130 |
5 |
5 |
100.00 |
| IF |
135 |
5 |
5 |
100.00 |
| IF |
140 |
2 |
2 |
100.00 |
| CASE |
155 |
6 |
6 |
100.00 |
| IF |
172 |
5 |
5 |
100.00 |
| IF |
201 |
2 |
2 |
100.00 |
| CASE |
226 |
33 |
32 |
96.97 |
| IF |
302 |
2 |
2 |
100.00 |
83 if (shift_ir) begin
-1-
84 jtag_ir_shift_d = {td_i, jtag_ir_shift_q[IrLength-1:1]};
==>
85 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
88 if (capture_ir) begin
-1-
89 jtag_ir_shift_d = IrLength'(4'b0101);
==>
90 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
93 if (update_ir) begin
-1-
94 jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
==>
95 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
97 if (test_logic_reset) begin
-1-
98 // Bring all TAP state to the initial value.
99 jtag_ir_shift_d = '0;
==>
100 jtag_ir_d = IDCODE;
101 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
105 if (!trst_ni) begin
-1-
106 jtag_ir_shift_q <= '0;
==>
107 jtag_ir_q <= IDCODE;
108 end else begin
109 jtag_ir_shift_q <= jtag_ir_shift_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
130 if (capture_dr) begin
-1-
131 if (idcode_select) idcode_d = IdcodeValue;
-2-
==>
MISSING_ELSE
==>
132 if (bypass_select) bypass_d = 1'b0;
-3-
==>
MISSING_ELSE
==>
133 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T1,T2,T3 |
| 1 |
0 |
- |
Covered |
T1,T2,T3 |
| 1 |
- |
1 |
Covered |
T1,T2,T3 |
| 1 |
- |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
Covered |
T1,T2,T3 |
135 if (shift_dr) begin
-1-
136 if (idcode_select) idcode_d = {td_i, 31'(idcode_q >> 1)};
-2-
==>
MISSING_ELSE
==>
137 if (bypass_select) bypass_d = td_i;
-3-
==>
MISSING_ELSE
==>
138 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T1,T2,T3 |
| 1 |
0 |
- |
Covered |
T1,T2,T3 |
| 1 |
- |
1 |
Covered |
T1,T2,T3 |
| 1 |
- |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
Covered |
T1,T2,T3 |
140 if (test_logic_reset) begin
-1-
141 // Bring all TAP state to the initial value.
142 idcode_d = IdcodeValue;
==>
143 bypass_d = 1'b0;
144 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
155 unique case (jtag_ir_q)
-1-
156 BYPASS0: bypass_select = 1'b1;
==>
157 IDCODE: idcode_select = 1'b1;
==>
158 DTMCSR: dtmcs_select_o = 1'b1;
==>
159 DMIACCESS: dmi_select_o = 1'b1;
==>
160 BYPASS1: bypass_select = 1'b1;
==>
161 default: bypass_select = 1'b1;
==>
Branches:
| -1- | Status | Tests |
| BYPASS0 |
Covered |
T89,T82,T96 |
| IDCODE |
Covered |
T1,T2,T3 |
| DTMCSR |
Covered |
T3,T13,T36 |
| DMIACCESS |
Covered |
T1,T2,T3 |
| BYPASS1 |
Covered |
T96,T97,T98 |
| default |
Covered |
T64,T15,T82 |
172 if (shift_ir) begin
-1-
173 tdo_mux = jtag_ir_shift_q[0];
==>
174 // here we are shifting the DR register
175 end else begin
176 unique case (jtag_ir_q)
-2-
177 IDCODE: tdo_mux = idcode_q[0]; // Reading ID code
==>
178 DTMCSR: tdo_mux = dtmcs_tdo_i; // Read from DTMCS TDO
==>
179 DMIACCESS: tdo_mux = dmi_tdo_i; // Read from DMI TDO
==>
180 default: tdo_mux = bypass_q; // BYPASS instruction
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
IDCODE |
Covered |
T1,T2,T3 |
| 0 |
DTMCSR |
Covered |
T3,T13,T36 |
| 0 |
DMIACCESS |
Covered |
T1,T2,T3 |
| 0 |
default |
Covered |
T64,T15,T89 |
201 if (!trst_ni) begin
-1-
202 td_o <= 1'b0;
==>
203 tdo_oe_o <= 1'b0;
204 end else begin
205 td_o <= tdo_mux;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
226 unique case (tap_state_q)
-1-
227 TestLogicReset: begin
228 tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
-2-
==>
==>
229 test_logic_reset = 1'b1;
230 end
231 RunTestIdle: begin
232 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
-3-
==>
==>
233 end
234 // DR Path
235 SelectDrScan: begin
236 tap_state_d = (tms_i) ? SelectIrScan : CaptureDr;
-4-
==>
==>
237 end
238 CaptureDr: begin
239 capture_dr = 1'b1;
240 tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
-5-
==>
==>
241 end
242 ShiftDr: begin
243 shift_dr = 1'b1;
244 tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
-6-
==>
==>
245 end
246 Exit1Dr: begin
247 tap_state_d = (tms_i) ? UpdateDr : PauseDr;
-7-
==>
==>
248 end
249 PauseDr: begin
250 tap_state_d = (tms_i) ? Exit2Dr : PauseDr;
-8-
==>
==>
251 end
252 Exit2Dr: begin
253 tap_state_d = (tms_i) ? UpdateDr : ShiftDr;
-9-
==>
==>
254 end
255 UpdateDr: begin
256 update_dr = 1'b1;
257 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
-10-
==>
==>
258 end
259 // IR Path
260 SelectIrScan: begin
261 tap_state_d = (tms_i) ? TestLogicReset : CaptureIr;
-11-
==>
==>
262 end
263 // In this controller state, the shift register bank in the
264 // Instruction Register parallel loads a pattern of fixed values on
265 // the rising edge of TCK. The last two significant bits must always
266 // be "01".
267 CaptureIr: begin
268 capture_ir = 1'b1;
269 tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
-12-
==>
==>
270 end
271 // In this controller state, the instruction register gets connected
272 // between TDI and TDO, and the captured pattern gets shifted on
273 // each rising edge of TCK. The instruction available on the TDI
274 // pin is also shifted in to the instruction register.
275 ShiftIr: begin
276 shift_ir = 1'b1;
277 tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
-13-
==>
==>
278 end
279 Exit1Ir: begin
280 tap_state_d = (tms_i) ? UpdateIr : PauseIr;
-14-
==>
==>
281 end
282 PauseIr: begin
283 // pause_ir = 1'b1; // unused
284 tap_state_d = (tms_i) ? Exit2Ir : PauseIr;
-15-
==>
==>
285 end
286 Exit2Ir: begin
287 tap_state_d = (tms_i) ? UpdateIr : ShiftIr;
-16-
==>
==>
288 end
289 // In this controller state, the instruction in the instruction
290 // shift register is latched to the latch bank of the Instruction
291 // Register on every falling edge of TCK. This instruction becomes
292 // the current instruction once it is latched.
293 UpdateIr: begin
294 update_ir = 1'b1;
295 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
-17-
==>
==>
296 end
297 default: ; // can't actually happen since case is full
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | Status | Tests |
| TestLogicReset |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T89,T82 |
| TestLogicReset |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| RunTestIdle |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| RunTestIdle |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| SelectDrScan |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| SelectDrScan |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| CaptureDr |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T82,T99,T100 |
| CaptureDr |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ShiftDr |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ShiftDr |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| Exit1Dr |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| Exit1Dr |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| PauseDr |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| PauseDr |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| Exit2Dr |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| Exit2Dr |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| UpdateDr |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| UpdateDr |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| SelectIrScan |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| SelectIrScan |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| CaptureIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T64,T15,T82 |
| CaptureIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ShiftIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| ShiftIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| Exit1Ir |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| Exit1Ir |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| PauseIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T1,T6,T12 |
| PauseIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
| Exit2Ir |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T6,T12 |
| Exit2Ir |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T1,T2,T3 |
| UpdateIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
| UpdateIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
302 if (!trst_ni) begin
-1-
303 tap_state_q <= TestLogicReset;
==>
304 idcode_q <= IdcodeValue;
305 bypass_q <= 1'b0;
306 end else begin
307 tap_state_q <= tap_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 96 | 96 | 100.00 |
| ALWAYS | 79 | 11 | 11 | 100.00 |
| ALWAYS | 105 | 5 | 5 | 100.00 |
| ALWAYS | 127 | 15 | 15 | 100.00 |
| ALWAYS | 151 | 10 | 10 | 100.00 |
| ALWAYS | 172 | 6 | 6 | 100.00 |
| ALWAYS | 201 | 5 | 5 | 100.00 |
| ALWAYS | 215 | 31 | 31 | 100.00 |
| ALWAYS | 302 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 315 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 318 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 319 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 320 | 1 | 1 | 100.00 |
78 always_comb begin : p_jtag
79 1/1 jtag_ir_shift_d = jtag_ir_shift_q;
Tests: T1 T2 T3
80 1/1 jtag_ir_d = jtag_ir_q;
Tests: T1 T2 T3
81
82 // IR shift register
83 1/1 if (shift_ir) begin
Tests: T1 T2 T3
84 1/1 jtag_ir_shift_d = {td_i, jtag_ir_shift_q[IrLength-1:1]};
Tests: T1 T2 T3
85 end
MISSING_ELSE
86
87 // capture IR register
88 1/1 if (capture_ir) begin
Tests: T1 T2 T3
89 1/1 jtag_ir_shift_d = IrLength'(4'b0101);
Tests: T1 T2 T3
90 end
MISSING_ELSE
91
92 // update IR register
93 1/1 if (update_ir) begin
Tests: T1 T2 T3
94 1/1 jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
Tests: T1 T2 T3
95 end
MISSING_ELSE
96
97 1/1 if (test_logic_reset) begin
Tests: T1 T2 T3
98 // Bring all TAP state to the initial value.
99 1/1 jtag_ir_shift_d = '0;
Tests: T1 T2 T3
100 1/1 jtag_ir_d = IDCODE;
Tests: T1 T2 T3
101 end
MISSING_ELSE
102 end
103
104 always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg
105 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
106 1/1 jtag_ir_shift_q <= '0;
Tests: T1 T2 T3
107 1/1 jtag_ir_q <= IDCODE;
Tests: T1 T2 T3
108 end else begin
109 1/1 jtag_ir_shift_q <= jtag_ir_shift_d;
Tests: T1 T2 T3
110 1/1 jtag_ir_q <= jtag_ir_d;
Tests: T1 T2 T3
111 end
112 end
113
114 // ----------------
115 // TAP DR Regs
116 // ----------------
117 // - Bypass
118 // - IDCODE
119 // - DTM CS
120 logic [31:0] idcode_d, idcode_q;
121 logic idcode_select;
122 logic bypass_select;
123
124 logic bypass_d, bypass_q; // this is a 1-bit register
125
126 always_comb begin
127 1/1 idcode_d = idcode_q;
Tests: T1 T2 T3
128 1/1 bypass_d = bypass_q;
Tests: T1 T2 T3
129
130 1/1 if (capture_dr) begin
Tests: T1 T2 T3
131 2/2 if (idcode_select) idcode_d = IdcodeValue;
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
132 2/2 if (bypass_select) bypass_d = 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
133 end
MISSING_ELSE
134
135 1/1 if (shift_dr) begin
Tests: T1 T2 T3
136 2/2 if (idcode_select) idcode_d = {td_i, 31'(idcode_q >> 1)};
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
137 2/2 if (bypass_select) bypass_d = td_i;
Tests: T1 T2 T3 | T1 T2 T3
MISSING_ELSE
138 end
MISSING_ELSE
139
140 1/1 if (test_logic_reset) begin
Tests: T1 T2 T3
141 // Bring all TAP state to the initial value.
142 1/1 idcode_d = IdcodeValue;
Tests: T1 T2 T3
143 1/1 bypass_d = 1'b0;
Tests: T1 T2 T3
144 end
MISSING_ELSE
145 end
146
147 // ----------------
148 // Data reg select
149 // ----------------
150 always_comb begin : p_data_reg_sel
151 1/1 dmi_select_o = 1'b0;
Tests: T1 T2 T3
152 1/1 dtmcs_select_o = 1'b0;
Tests: T1 T2 T3
153 1/1 idcode_select = 1'b0;
Tests: T1 T2 T3
154 1/1 bypass_select = 1'b0;
Tests: T1 T2 T3
155 1/1 unique case (jtag_ir_q)
Tests: T1 T2 T3
156 1/1 BYPASS0: bypass_select = 1'b1;
Tests: T89 T82 T96
157 1/1 IDCODE: idcode_select = 1'b1;
Tests: T1 T2 T3
158 1/1 DTMCSR: dtmcs_select_o = 1'b1;
Tests: T3 T13 T36
159 1/1 DMIACCESS: dmi_select_o = 1'b1;
Tests: T1 T2 T3
160 1/1 BYPASS1: bypass_select = 1'b1;
Tests: T96 T97 T98
161 default: bypass_select = 1'b1;
162 endcase
163 end
164
165 // ----------------
166 // Output select
167 // ----------------
168 logic tdo_mux;
169
170 always_comb begin : p_out_sel
171 // we are shifting out the IR register
172 1/1 if (shift_ir) begin
Tests: T1 T2 T3
173 1/1 tdo_mux = jtag_ir_shift_q[0];
Tests: T1 T2 T3
174 // here we are shifting the DR register
175 end else begin
176 1/1 unique case (jtag_ir_q)
Tests: T1 T2 T3
177 1/1 IDCODE: tdo_mux = idcode_q[0]; // Reading ID code
Tests: T1 T2 T3
178 1/1 DTMCSR: tdo_mux = dtmcs_tdo_i; // Read from DTMCS TDO
Tests: T3 T13 T36
179 1/1 DMIACCESS: tdo_mux = dmi_tdo_i; // Read from DMI TDO
Tests: T1 T2 T3
180 default: tdo_mux = bypass_q; // BYPASS instruction
181 endcase
182 end
183 end
184
185 // ----------------
186 // DFT
187 // ----------------
188 logic tck_n;
189
190 prim_clock_inv #(
191 .HasScanMode(1'b1),
192 .NoFpgaBufG(1'b1)
193 ) i_tck_inv (
194 .clk_i ( tck_i ),
195 .clk_no ( tck_n ),
196 .scanmode_i ( testmode_i )
197 );
198
199 // TDO changes state at negative edge of TCK
200 always_ff @(posedge tck_n, negedge trst_ni) begin : p_tdo_regs
201 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
202 1/1 td_o <= 1'b0;
Tests: T1 T2 T3
203 1/1 tdo_oe_o <= 1'b0;
Tests: T1 T2 T3
204 end else begin
205 1/1 td_o <= tdo_mux;
Tests: T1 T2 T3
206 1/1 tdo_oe_o <= (shift_ir | shift_dr);
Tests: T1 T2 T3
207 end
208 end
209 // ----------------
210 // TAP FSM
211 // ----------------
212 // Determination of next state; purely combinatorial
213 always_comb begin : p_tap_fsm
214
215 1/1 test_logic_reset = 1'b0;
Tests: T1 T2 T3
216
217 1/1 capture_dr = 1'b0;
Tests: T1 T2 T3
218 1/1 shift_dr = 1'b0;
Tests: T1 T2 T3
219 1/1 update_dr = 1'b0;
Tests: T1 T2 T3
220
221 1/1 capture_ir = 1'b0;
Tests: T1 T2 T3
222 1/1 shift_ir = 1'b0;
Tests: T1 T2 T3
223 // pause_ir = 1'b0; unused
224 1/1 update_ir = 1'b0;
Tests: T1 T2 T3
225
226 1/1 unique case (tap_state_q)
Tests: T1 T2 T3
227 TestLogicReset: begin
228 1/1 tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
Tests: T1 T2 T3
229 1/1 test_logic_reset = 1'b1;
Tests: T1 T2 T3
230 end
231 RunTestIdle: begin
232 1/1 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
Tests: T1 T2 T3
233 end
234 // DR Path
235 SelectDrScan: begin
236 1/1 tap_state_d = (tms_i) ? SelectIrScan : CaptureDr;
Tests: T1 T2 T3
237 end
238 CaptureDr: begin
239 1/1 capture_dr = 1'b1;
Tests: T1 T2 T3
240 1/1 tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
Tests: T1 T2 T3
241 end
242 ShiftDr: begin
243 1/1 shift_dr = 1'b1;
Tests: T1 T2 T3
244 1/1 tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
Tests: T1 T2 T3
245 end
246 Exit1Dr: begin
247 1/1 tap_state_d = (tms_i) ? UpdateDr : PauseDr;
Tests: T1 T2 T3
248 end
249 PauseDr: begin
250 1/1 tap_state_d = (tms_i) ? Exit2Dr : PauseDr;
Tests: T1 T2 T3
251 end
252 Exit2Dr: begin
253 1/1 tap_state_d = (tms_i) ? UpdateDr : ShiftDr;
Tests: T1 T2 T3
254 end
255 UpdateDr: begin
256 1/1 update_dr = 1'b1;
Tests: T1 T2 T3
257 1/1 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
Tests: T1 T2 T3
258 end
259 // IR Path
260 SelectIrScan: begin
261 1/1 tap_state_d = (tms_i) ? TestLogicReset : CaptureIr;
Tests: T1 T2 T3
262 end
263 // In this controller state, the shift register bank in the
264 // Instruction Register parallel loads a pattern of fixed values on
265 // the rising edge of TCK. The last two significant bits must always
266 // be "01".
267 CaptureIr: begin
268 1/1 capture_ir = 1'b1;
Tests: T1 T2 T3
269 1/1 tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
Tests: T1 T2 T3
270 end
271 // In this controller state, the instruction register gets connected
272 // between TDI and TDO, and the captured pattern gets shifted on
273 // each rising edge of TCK. The instruction available on the TDI
274 // pin is also shifted in to the instruction register.
275 ShiftIr: begin
276 1/1 shift_ir = 1'b1;
Tests: T1 T2 T3
277 1/1 tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
Tests: T1 T2 T3
278 end
279 Exit1Ir: begin
280 1/1 tap_state_d = (tms_i) ? UpdateIr : PauseIr;
Tests: T1 T2 T3
281 end
282 PauseIr: begin
283 // pause_ir = 1'b1; // unused
284 1/1 tap_state_d = (tms_i) ? Exit2Ir : PauseIr;
Tests: T1 T2 T3
285 end
286 Exit2Ir: begin
287 1/1 tap_state_d = (tms_i) ? UpdateIr : ShiftIr;
Tests: T1 T2 T3
288 end
289 // In this controller state, the instruction in the instruction
290 // shift register is latched to the latch bank of the Instruction
291 // Register on every falling edge of TCK. This instruction becomes
292 // the current instruction once it is latched.
293 UpdateIr: begin
294 1/1 update_ir = 1'b1;
Tests: T1 T2 T3
295 1/1 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
Tests: T1 T2 T3
296 end
297 default: ; // can't actually happen since case is full
Exclude Annotation: VC_COV_UNR
298 endcase
299 end
300
301 always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
302 1/1 if (!trst_ni) begin
Tests: T1 T2 T3
303 1/1 tap_state_q <= TestLogicReset;
Tests: T1 T2 T3
304 1/1 idcode_q <= IdcodeValue;
Tests: T1 T2 T3
305 1/1 bypass_q <= 1'b0;
Tests: T1 T2 T3
306 end else begin
307 1/1 tap_state_q <= tap_state_d;
Tests: T1 T2 T3
308 1/1 idcode_q <= idcode_d;
Tests: T1 T2 T3
309 1/1 bypass_q <= bypass_d;
Tests: T1 T2 T3
310 end
311 end
312
313 // Pass through JTAG signals to debug custom DR logic.
314 // In case of a single TAP those are just feed-through.
315 1/1 assign tck_o = tck_i;
Tests: T1 T2 T3
316 1/1 assign tdi_o = td_i;
Tests: T1 T2 T3
317 1/1 assign update_o = update_dr;
Tests: T1 T2 T3
318 1/1 assign shift_o = shift_dr;
Tests: T1 T2 T3
319 1/1 assign capture_o = capture_dr;
Tests: T1 T2 T3
320 1/1 assign dmi_clear_o = test_logic_reset;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap
| Total | Covered | Percent |
|---|
| Conditions | 35 | 35 | 100.00 |
| Logical | 35 | 35 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 206
EXPRESSION (shift_ir | shift_dr)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 228
EXPRESSION (tms_i ? TestLogicReset : RunTestIdle)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T89,T82 |
LINE 232
EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 236
EXPRESSION (tms_i ? SelectIrScan : CaptureDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 240
EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T82,T99,T100 |
LINE 244
EXPRESSION (tms_i ? Exit1Dr : ShiftDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (tms_i ? UpdateDr : PauseDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 250
EXPRESSION (tms_i ? Exit2Dr : PauseDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 253
EXPRESSION (tms_i ? UpdateDr : ShiftDr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 257
EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 261
EXPRESSION (tms_i ? TestLogicReset : CaptureIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 269
EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T64,T15,T82 |
LINE 277
EXPRESSION (tms_i ? Exit1Ir : ShiftIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 280
EXPRESSION (tms_i ? UpdateIr : PauseIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 284
EXPRESSION (tms_i ? Exit2Ir : PauseIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T12 |
LINE 287
EXPRESSION (tms_i ? UpdateIr : ShiftIr)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T6,T12 |
LINE 295
EXPRESSION (tms_i ? SelectDrScan : RunTestIdle)
--1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap
Summary for FSM :: tap_state_q
| Total | Covered | Percent | |
| States |
16 |
16 |
100.00 |
(Not included in score) |
| Transitions |
40 |
36 |
90.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: tap_state_q
| states | Line No. | Covered | Tests |
| CaptureDr |
236 |
Covered |
T1,T2,T3 |
| CaptureIr |
261 |
Covered |
T1,T2,T3 |
| Exit1Dr |
240 |
Covered |
T1,T2,T3 |
| Exit1Ir |
269 |
Covered |
T1,T2,T3 |
| Exit2Dr |
250 |
Covered |
T1,T2,T3 |
| Exit2Ir |
284 |
Covered |
T1,T6,T12 |
| PauseDr |
247 |
Covered |
T1,T2,T3 |
| PauseIr |
280 |
Covered |
T1,T6,T12 |
| RunTestIdle |
228 |
Covered |
T1,T2,T3 |
| SelectDrScan |
232 |
Covered |
T1,T2,T3 |
| SelectIrScan |
236 |
Covered |
T1,T2,T3 |
| ShiftDr |
240 |
Covered |
T1,T2,T3 |
| ShiftIr |
269 |
Covered |
T1,T2,T3 |
| TestLogicReset |
303 |
Covered |
T1,T2,T3 |
| UpdateDr |
247 |
Covered |
T1,T2,T3 |
| UpdateIr |
280 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| CaptureDr->Exit1Dr |
240 |
Covered |
T82,T99,T100 |
| CaptureDr->ShiftDr |
240 |
Covered |
T1,T2,T3 |
| CaptureDr->TestLogicReset |
303 |
Covered |
T99 |
| CaptureIr->Exit1Ir |
269 |
Covered |
T64,T15,T82 |
| CaptureIr->ShiftIr |
269 |
Covered |
T1,T2,T3 |
| CaptureIr->TestLogicReset |
303 |
Covered |
T101,T102,T103 |
| Exit1Dr->PauseDr |
247 |
Covered |
T1,T2,T3 |
| Exit1Dr->TestLogicReset |
303 |
Not Covered |
|
| Exit1Dr->UpdateDr |
247 |
Covered |
T1,T2,T3 |
| Exit1Ir->PauseIr |
280 |
Covered |
T1,T6,T12 |
| Exit1Ir->TestLogicReset |
303 |
Covered |
T103,T104,T105 |
| Exit1Ir->UpdateIr |
280 |
Covered |
T1,T2,T3 |
| Exit2Dr->ShiftDr |
253 |
Covered |
T1,T2,T3 |
| Exit2Dr->TestLogicReset |
303 |
Covered |
T106 |
| Exit2Dr->UpdateDr |
253 |
Covered |
T1,T2,T12 |
| Exit2Ir->ShiftIr |
287 |
Covered |
T1,T6,T12 |
| Exit2Ir->TestLogicReset |
303 |
Not Covered |
|
| Exit2Ir->UpdateIr |
287 |
Covered |
T12,T8,T27 |
| PauseDr->Exit2Dr |
250 |
Covered |
T1,T2,T3 |
| PauseDr->TestLogicReset |
303 |
Covered |
T107,T101,T106 |
| PauseIr->Exit2Ir |
284 |
Covered |
T1,T6,T12 |
| PauseIr->TestLogicReset |
303 |
Covered |
T108,T109,T101 |
| RunTestIdle->SelectDrScan |
232 |
Covered |
T1,T2,T3 |
| RunTestIdle->TestLogicReset |
303 |
Covered |
T7,T46,T24 |
| SelectDrScan->CaptureDr |
236 |
Covered |
T1,T2,T3 |
| SelectDrScan->SelectIrScan |
236 |
Covered |
T1,T2,T3 |
| SelectDrScan->TestLogicReset |
303 |
Covered |
T70,T106,T105 |
| SelectIrScan->CaptureIr |
261 |
Covered |
T1,T2,T3 |
| SelectIrScan->TestLogicReset |
303 |
Covered |
T89,T82,T34 |
| ShiftDr->Exit1Dr |
244 |
Covered |
T1,T2,T3 |
| ShiftDr->TestLogicReset |
303 |
Covered |
T61,T69,T70 |
| ShiftIr->Exit1Ir |
277 |
Covered |
T1,T2,T3 |
| ShiftIr->TestLogicReset |
303 |
Covered |
T61,T108,T101 |
| TestLogicReset->RunTestIdle |
228 |
Covered |
T1,T2,T3 |
| UpdateDr->RunTestIdle |
257 |
Covered |
T1,T2,T3 |
| UpdateDr->SelectDrScan |
257 |
Not Covered |
|
| UpdateDr->TestLogicReset |
303 |
Covered |
T82,T71,T26 |
| UpdateIr->RunTestIdle |
295 |
Covered |
T1,T2,T3 |
| UpdateIr->SelectDrScan |
295 |
Not Covered |
|
| UpdateIr->TestLogicReset |
303 |
Covered |
T110,T100,T111 |
Branch Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap
| Line No. | Total | Covered | Percent |
| Branches |
|
69 |
69 |
100.00 |
| IF |
83 |
2 |
2 |
100.00 |
| IF |
88 |
2 |
2 |
100.00 |
| IF |
93 |
2 |
2 |
100.00 |
| IF |
97 |
2 |
2 |
100.00 |
| IF |
105 |
2 |
2 |
100.00 |
| IF |
130 |
5 |
5 |
100.00 |
| IF |
135 |
5 |
5 |
100.00 |
| IF |
140 |
2 |
2 |
100.00 |
| CASE |
155 |
6 |
6 |
100.00 |
| IF |
172 |
5 |
5 |
100.00 |
| IF |
201 |
2 |
2 |
100.00 |
| CASE |
226 |
32 |
32 |
100.00 |
| IF |
302 |
2 |
2 |
100.00 |
83 if (shift_ir) begin
-1-
84 jtag_ir_shift_d = {td_i, jtag_ir_shift_q[IrLength-1:1]};
==>
85 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
88 if (capture_ir) begin
-1-
89 jtag_ir_shift_d = IrLength'(4'b0101);
==>
90 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
93 if (update_ir) begin
-1-
94 jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
==>
95 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
97 if (test_logic_reset) begin
-1-
98 // Bring all TAP state to the initial value.
99 jtag_ir_shift_d = '0;
==>
100 jtag_ir_d = IDCODE;
101 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
105 if (!trst_ni) begin
-1-
106 jtag_ir_shift_q <= '0;
==>
107 jtag_ir_q <= IDCODE;
108 end else begin
109 jtag_ir_shift_q <= jtag_ir_shift_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
130 if (capture_dr) begin
-1-
131 if (idcode_select) idcode_d = IdcodeValue;
-2-
==>
MISSING_ELSE
==>
132 if (bypass_select) bypass_d = 1'b0;
-3-
==>
MISSING_ELSE
==>
133 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T1,T2,T3 |
| 1 |
0 |
- |
Covered |
T1,T2,T3 |
| 1 |
- |
1 |
Covered |
T1,T2,T3 |
| 1 |
- |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
Covered |
T1,T2,T3 |
135 if (shift_dr) begin
-1-
136 if (idcode_select) idcode_d = {td_i, 31'(idcode_q >> 1)};
-2-
==>
MISSING_ELSE
==>
137 if (bypass_select) bypass_d = td_i;
-3-
==>
MISSING_ELSE
==>
138 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T1,T2,T3 |
| 1 |
0 |
- |
Covered |
T1,T2,T3 |
| 1 |
- |
1 |
Covered |
T1,T2,T3 |
| 1 |
- |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
- |
Covered |
T1,T2,T3 |
140 if (test_logic_reset) begin
-1-
141 // Bring all TAP state to the initial value.
142 idcode_d = IdcodeValue;
==>
143 bypass_d = 1'b0;
144 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
155 unique case (jtag_ir_q)
-1-
156 BYPASS0: bypass_select = 1'b1;
==>
157 IDCODE: idcode_select = 1'b1;
==>
158 DTMCSR: dtmcs_select_o = 1'b1;
==>
159 DMIACCESS: dmi_select_o = 1'b1;
==>
160 BYPASS1: bypass_select = 1'b1;
==>
161 default: bypass_select = 1'b1;
==>
Branches:
| -1- | Status | Tests |
| BYPASS0 |
Covered |
T89,T82,T96 |
| IDCODE |
Covered |
T1,T2,T3 |
| DTMCSR |
Covered |
T3,T13,T36 |
| DMIACCESS |
Covered |
T1,T2,T3 |
| BYPASS1 |
Covered |
T96,T97,T98 |
| default |
Covered |
T64,T15,T82 |
172 if (shift_ir) begin
-1-
173 tdo_mux = jtag_ir_shift_q[0];
==>
174 // here we are shifting the DR register
175 end else begin
176 unique case (jtag_ir_q)
-2-
177 IDCODE: tdo_mux = idcode_q[0]; // Reading ID code
==>
178 DTMCSR: tdo_mux = dtmcs_tdo_i; // Read from DTMCS TDO
==>
179 DMIACCESS: tdo_mux = dmi_tdo_i; // Read from DMI TDO
==>
180 default: tdo_mux = bypass_q; // BYPASS instruction
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
IDCODE |
Covered |
T1,T2,T3 |
| 0 |
DTMCSR |
Covered |
T3,T13,T36 |
| 0 |
DMIACCESS |
Covered |
T1,T2,T3 |
| 0 |
default |
Covered |
T64,T15,T89 |
201 if (!trst_ni) begin
-1-
202 td_o <= 1'b0;
==>
203 tdo_oe_o <= 1'b0;
204 end else begin
205 td_o <= tdo_mux;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
226 unique case (tap_state_q)
-1-
227 TestLogicReset: begin
228 tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
-2-
==>
==>
229 test_logic_reset = 1'b1;
230 end
231 RunTestIdle: begin
232 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
-3-
==>
==>
233 end
234 // DR Path
235 SelectDrScan: begin
236 tap_state_d = (tms_i) ? SelectIrScan : CaptureDr;
-4-
==>
==>
237 end
238 CaptureDr: begin
239 capture_dr = 1'b1;
240 tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
-5-
==>
==>
241 end
242 ShiftDr: begin
243 shift_dr = 1'b1;
244 tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
-6-
==>
==>
245 end
246 Exit1Dr: begin
247 tap_state_d = (tms_i) ? UpdateDr : PauseDr;
-7-
==>
==>
248 end
249 PauseDr: begin
250 tap_state_d = (tms_i) ? Exit2Dr : PauseDr;
-8-
==>
==>
251 end
252 Exit2Dr: begin
253 tap_state_d = (tms_i) ? UpdateDr : ShiftDr;
-9-
==>
==>
254 end
255 UpdateDr: begin
256 update_dr = 1'b1;
257 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
-10-
==>
==>
258 end
259 // IR Path
260 SelectIrScan: begin
261 tap_state_d = (tms_i) ? TestLogicReset : CaptureIr;
-11-
==>
==>
262 end
263 // In this controller state, the shift register bank in the
264 // Instruction Register parallel loads a pattern of fixed values on
265 // the rising edge of TCK. The last two significant bits must always
266 // be "01".
267 CaptureIr: begin
268 capture_ir = 1'b1;
269 tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
-12-
==>
==>
270 end
271 // In this controller state, the instruction register gets connected
272 // between TDI and TDO, and the captured pattern gets shifted on
273 // each rising edge of TCK. The instruction available on the TDI
274 // pin is also shifted in to the instruction register.
275 ShiftIr: begin
276 shift_ir = 1'b1;
277 tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
-13-
==>
==>
278 end
279 Exit1Ir: begin
280 tap_state_d = (tms_i) ? UpdateIr : PauseIr;
-14-
==>
==>
281 end
282 PauseIr: begin
283 // pause_ir = 1'b1; // unused
284 tap_state_d = (tms_i) ? Exit2Ir : PauseIr;
-15-
==>
==>
285 end
286 Exit2Ir: begin
287 tap_state_d = (tms_i) ? UpdateIr : ShiftIr;
-16-
==>
==>
288 end
289 // In this controller state, the instruction in the instruction
290 // shift register is latched to the latch bank of the Instruction
291 // Register on every falling edge of TCK. This instruction becomes
292 // the current instruction once it is latched.
293 UpdateIr: begin
294 update_ir = 1'b1;
295 tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
-17-
==>
==>
296 end
297 default: ; // can't actually happen since case is full
==> (Excluded)
Exclude Annotation: VC_COV_UNR
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | Status | Tests | Exclude Annotation |
| TestLogicReset |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T89,T82 |
|
| TestLogicReset |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| RunTestIdle |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| RunTestIdle |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| SelectDrScan |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| SelectDrScan |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| CaptureDr |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T82,T99,T100 |
|
| CaptureDr |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ShiftDr |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ShiftDr |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| Exit1Dr |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| Exit1Dr |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| PauseDr |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| PauseDr |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| Exit2Dr |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| Exit2Dr |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| UpdateDr |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| UpdateDr |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| SelectIrScan |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| SelectIrScan |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| CaptureIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T64,T15,T82 |
|
| CaptureIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ShiftIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| ShiftIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| Exit1Ir |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| Exit1Ir |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
|
| PauseIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T1,T6,T12 |
|
| PauseIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
|
| Exit2Ir |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T1,T6,T12 |
|
| Exit2Ir |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
Covered |
T1,T2,T3 |
|
| UpdateIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T2,T3 |
|
| UpdateIr |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
|
| default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
302 if (!trst_ni) begin
-1-
303 tap_state_q <= TestLogicReset;
==>
304 idcode_q <= IdcodeValue;
305 bypass_q <= 1'b0;
306 end else begin
307 tap_state_q <= tap_state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |