Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T89

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T89
1	1	Covered	T89

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8319086	8317598	0	0
selKnown1	69422112	69420624	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8319086	8317598	0	0
T1	7534	7532	0	0
T2	1842	1840	0	0
T3	1800	1798	0	0
T4	742	740	0	0
T5	2974	2972	0	0
T6	682	680	0	0
T7	4	2	0	0
T8	3	1	0	0
T12	1640	1638	0	0
T13	2678	2676	0	0
T15	0	5	0	0
T18	12270	12268	0	0
T19	2	0	0	0
T24	4	2	0	0
T36	2	0	0	0
T43	0	2	0	0
T45	1166	1164	0	0
T46	4	2	0	0
T47	0	20	0	0
T59	2	0	0	0
T62	2	0	0	0
T64	2	0	0	0
T74	0	1	0	0
T79	0	8	0	0
T82	0	9	0	0
T83	2	0	0	0
T89	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	69422112	69420624	0	0
T1	19588	19586	0	0
T2	10733	10731	0	0
T3	19623	19621	0	0
T4	31697	31695	0	0
T5	45463	45461	0	0
T6	2000	1998	0	0
T12	30807	30805	0	0
T13	35631	35629	0	0
T15	4	2	0	0
T18	64379	64377	0	0
T20	2	0	0	0
T24	2	0	0	0
T27	2	0	0	0
T39	2	0	0	0
T42	0	4	0	0
T43	0	2	0	0
T45	25376	25374	0	0
T46	4	2	0	0
T47	22	20	0	0
T48	2	0	0	0
T51	0	2	0	0
T77	0	2	0	0
T79	0	8	0	0
T82	0	8	0	0
T83	2	0	0	0
T84	0	20	0	0
T89	2	0	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T89

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T89
1	1	Covered	T89

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2828374	2828112	0	0
selKnown1	63931491	63931229	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2828374	2828112	0	0
T1	3767	3766	0	0
T2	921	920	0	0
T3	900	899	0	0
T4	371	370	0	0
T5	1487	1486	0	0
T6	341	340	0	0
T12	820	819	0	0
T13	1339	1338	0	0
T18	6135	6134	0	0
T45	583	582	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	63931491	63931229	0	0
T1	15821	15820	0	0
T2	9812	9811	0	0
T3	18723	18722	0	0
T4	31326	31325	0	0
T5	43976	43975	0	0
T6	1659	1658	0	0
T12	29987	29986	0	0
T13	34292	34291	0	0
T18	58244	58243	0	0
T45	24793	24792	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T89

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T89
1	1	Covered	T89

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	752	490	0	0
selKnown1	710	448	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	752	490	0	0
T7	2	1	0	0
T8	1	0	0	0
T15	0	1	0	0
T19	1	0	0	0
T24	2	1	0	0
T36	1	0	0	0
T43	0	1	0	0
T46	2	1	0	0
T47	0	10	0	0
T59	1	0	0	0
T62	1	0	0	0
T64	1	0	0	0
T74	0	1	0	0
T79	0	4	0	0
T82	0	4	0	0
T83	1	0	0	0
T87	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	710	448	0	0
T15	2	1	0	0
T20	1	0	0	0
T24	1	0	0	0
T27	1	0	0	0
T39	1	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	2	1	0	0
T47	11	10	0	0
T48	1	0	0	0
T51	0	1	0	0
T77	0	1	0	0
T79	0	4	0	0
T82	0	4	0	0
T83	1	0	0	0
T84	0	10	0	0
T89	1	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T89

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T89
1	1	Covered	T89

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	5488149	5487667	0	0
selKnown1	5488148	5487666	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	5488149	5487667	0	0
T1	3767	3766	0	0
T2	921	920	0	0
T3	900	899	0	0
T4	371	370	0	0
T5	1487	1486	0	0
T6	341	340	0	0
T12	820	819	0	0
T13	1339	1338	0	0
T18	6135	6134	0	0
T45	583	582	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	5488148	5487666	0	0
T1	3767	3766	0	0
T2	921	920	0	0
T3	900	899	0	0
T4	371	370	0	0
T5	1487	1486	0	0
T6	341	340	0	0
T12	820	819	0	0
T13	1339	1338	0	0
T18	6135	6134	0	0
T45	583	582	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T89

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T89
1	1	Covered	T89

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T89
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1811	1329	0	0
selKnown1	1763	1281	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1811	1329	0	0
T7	2	1	0	0
T8	2	1	0	0
T15	0	4	0	0
T19	1	0	0	0
T24	2	1	0	0
T36	1	0	0	0
T43	0	1	0	0
T46	2	1	0	0
T47	0	10	0	0
T59	1	0	0	0
T62	1	0	0	0
T64	1	0	0	0
T79	0	4	0	0
T82	0	5	0	0
T83	1	0	0	0
T89	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1763	1281	0	0
T15	2	1	0	0
T20	1	0	0	0
T24	1	0	0	0
T27	1	0	0	0
T39	1	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	2	1	0	0
T47	11	10	0	0
T48	1	0	0	0
T51	0	1	0	0
T77	0	1	0	0
T79	0	4	0	0
T82	0	4	0	0
T83	1	0	0	0
T84	0	10	0	0
T89	1	0	0	0