Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 90.48 97.60 100.00 93.75 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 90.48 97.60 100.00 93.75 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_en_sync_copies

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 90.48 97.60 100.00 93.75 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_pm_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 90.48 97.60 100.00 93.75 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.91 86.27 76.47 100.00 81.82 50.00 u_tlul_lc_gate_sba


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.00 100.00 100.00 100.00 100.00 50.00 u_tlul_lc_gate_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_dft_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00

67 always_ff @(posedge clk_i) begin 68 1/1 lc_en_in_sva_q <= lc_en_i; Tests: T1 T2 T3  69 end 70 `ASSERT(OutputDelay_A, 71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} || 72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1))) 73 `endif 74 end else begin : gen_no_flops 75 //VCS coverage off 76 // pragma coverage off 77 78 // This unused companion logic helps remove lint errors 79 // for modules where clock and reset are used for assertions only 80 // or nothing at all. 81 // This logic will be removed for sythesis since it is unloaded. 82 lc_ctrl_pkg::lc_tx_t unused_logic; 83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 if (!rst_ni) begin 85 unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 assign lc_en = lc_en_i; 94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_en_sync_copies

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00

83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 unreachable if (!rst_ni) begin 85 unreachable unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unreachable unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 1/1 assign lc_en = lc_en_i; Tests: T1 T2 T3  94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 5/5 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_pm_en_sync

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00

67 always_ff @(posedge clk_i) begin 68 1/1 lc_en_in_sva_q <= lc_en_i; Tests: T1 T2 T3  69 end 70 `ASSERT(OutputDelay_A, 71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} || 72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1))) 73 `endif 74 end else begin : gen_no_flops 75 //VCS coverage off 76 // pragma coverage off 77 78 // This unused companion logic helps remove lint errors 79 // for modules where clock and reset are used for assertions only 80 // or nothing at all. 81 // This logic will be removed for sythesis since it is unloaded. 82 lc_ctrl_pkg::lc_tx_t unused_logic; 83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 if (!rst_ni) begin 85 unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 assign lc_en = lc_en_i; 94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00

83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 unreachable if (!rst_ni) begin 85 unreachable unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unreachable unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 1/1 assign lc_en = lc_en_i; Tests: T1 T2 T3  94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1572 1572 0 0
OutputsKnown_A 383379296 383072660 0 0
gen_flops.OutputDelay_A 191794473 191634765 0 2358
gen_no_flops.OutputDelay_A 191584823 191431505 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1572 1572 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T12 6 6 0 0
T13 6 6 0 0
T18 6 6 0 0
T45 6 6 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 383379296 383072660 0 0
T1 94926 94554 0 0
T2 58872 58380 0 0
T3 112338 111906 0 0
T4 187956 187500 0 0
T5 263856 263478 0 0
T6 9954 9462 0 0
T12 179922 179496 0 0
T13 205752 205320 0 0
T18 349464 349050 0 0
T45 148758 148350 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191794473 191634765 0 2358
T1 47463 47268 0 9
T2 29436 29181 0 9
T3 56169 55944 0 9
T4 93978 93741 0 9
T5 131928 131730 0 9
T6 4977 4722 0 9
T12 89961 89739 0 9
T13 102876 102651 0 9
T18 174732 174516 0 9
T45 74379 74166 0 9

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 191584823 191431505 0 0
T1 47463 47277 0 0
T2 29436 29190 0 0
T3 56169 55953 0 0
T4 93978 93750 0 0
T5 131928 131739 0 0
T6 4977 4731 0 0
T12 89961 89748 0 0
T13 102876 102660 0 0
T18 174732 174525 0 0
T45 74379 74175 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00

67 always_ff @(posedge clk_i) begin 68 1/1 lc_en_in_sva_q <= lc_en_i; Tests: T1 T2 T3  69 end 70 `ASSERT(OutputDelay_A, 71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} || 72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1))) 73 `endif 74 end else begin : gen_no_flops 75 //VCS coverage off 76 // pragma coverage off 77 78 // This unused companion logic helps remove lint errors 79 // for modules where clock and reset are used for assertions only 80 // or nothing at all. 81 // This logic will be removed for sythesis since it is unloaded. 82 lc_ctrl_pkg::lc_tx_t unused_logic; 83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 if (!rst_ni) begin 85 unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 assign lc_en = lc_en_i; 94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 262 262 0 0
OutputsKnown_A 63931491 63880385 0 0
gen_flops.OutputDelay_A 63931491 63878255 0 786


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 262 262 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63880385 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63878255 0 786
T1 15821 15756 0 3
T2 9812 9727 0 3
T3 18723 18648 0 3
T4 31326 31247 0 3
T5 43976 43910 0 3
T6 1659 1574 0 3
T12 29987 29913 0 3
T13 34292 34217 0 3
T18 58244 58172 0 3
T45 24793 24722 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00

67 always_ff @(posedge clk_i) begin 68 1/1 lc_en_in_sva_q <= lc_en_i; Tests: T1 T2 T3  69 end 70 `ASSERT(OutputDelay_A, 71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} || 72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1))) 73 `endif 74 end else begin : gen_no_flops 75 //VCS coverage off 76 // pragma coverage off 77 78 // This unused companion logic helps remove lint errors 79 // for modules where clock and reset are used for assertions only 80 // or nothing at all. 81 // This logic will be removed for sythesis since it is unloaded. 82 lc_ctrl_pkg::lc_tx_t unused_logic; 83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 if (!rst_ni) begin 85 unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 assign lc_en = lc_en_i; 94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 262 262 0 0
OutputsKnown_A 63931491 63880385 0 0
gen_flops.OutputDelay_A 63931491 63878255 0 786


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 262 262 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63880385 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63878255 0 786
T1 15821 15756 0 3
T2 9812 9727 0 3
T3 18723 18648 0 3
T4 31326 31247 0 3
T5 43976 43910 0 3
T6 1659 1574 0 3
T12 29987 29913 0 3
T13 34292 34217 0 3
T18 58244 58172 0 3
T45 24793 24722 0 3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00

83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 unreachable if (!rst_ni) begin 85 unreachable unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unreachable unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 1/1 assign lc_en = lc_en_i; Tests: T1 T2 T3  94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 5/5 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 262 262 0 0
OutputsKnown_A 63721841 63670735 0 0
gen_no_flops.OutputDelay_A 63721841 63670735 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 262 262 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63721841 63670735 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63721841 63670735 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

Line Coverage for Instance : tb.dut.u_pm_en_sync
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00

67 always_ff @(posedge clk_i) begin 68 1/1 lc_en_in_sva_q <= lc_en_i; Tests: T1 T2 T3  69 end 70 `ASSERT(OutputDelay_A, 71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} || 72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1))) 73 `endif 74 end else begin : gen_no_flops 75 //VCS coverage off 76 // pragma coverage off 77 78 // This unused companion logic helps remove lint errors 79 // for modules where clock and reset are used for assertions only 80 // or nothing at all. 81 // This logic will be removed for sythesis since it is unloaded. 82 lc_ctrl_pkg::lc_tx_t unused_logic; 83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 if (!rst_ni) begin 85 unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 assign lc_en = lc_en_i; 94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_pm_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 262 262 0 0
OutputsKnown_A 63931491 63880385 0 0
gen_flops.OutputDelay_A 63931491 63878255 0 786


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 262 262 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63880385 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63878255 0 786
T1 15821 15756 0 3
T2 9812 9727 0 3
T3 18723 18648 0 3
T4 31326 31247 0 3
T5 43976 43910 0 3
T6 1659 1574 0 3
T12 29987 29913 0 3
T13 34292 34217 0 3
T18 58244 58172 0 3
T45 24793 24722 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00

83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 unreachable if (!rst_ni) begin 85 unreachable unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unreachable unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 1/1 assign lc_en = lc_en_i; Tests: T1 T2 T3  94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 262 262 0 0
OutputsKnown_A 63931491 63880385 0 0
gen_no_flops.OutputDelay_A 63931491 63880385 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 262 262 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63880385 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63880385 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00

83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 unreachable if (!rst_ni) begin 85 unreachable unused_logic <= lc_ctrl_pkg::Off; 86 end else begin 87 unreachable unused_logic <= lc_en_i; 88 end 89 end 90 //VCS coverage on 91 // pragma coverage on 92 93 1/1 assign lc_en = lc_en_i; Tests: T1 T2 T3  94 95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) 96 end 97 98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; 100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 101 prim_sec_anchor_buf u_prim_buf ( 102 .in_i(lc_en[k]), 103 .out_o(lc_en_out[k]) 104 ); 105 end 106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3  | T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 262 262 0 0
OutputsKnown_A 63931491 63880385 0 0
gen_no_flops.OutputDelay_A 63931491 63880385 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 262 262 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63880385 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63931491 63880385 0 0
T1 15821 15759 0 0
T2 9812 9730 0 0
T3 18723 18651 0 0
T4 31326 31250 0 0
T5 43976 43913 0 0
T6 1659 1577 0 0
T12 29987 29916 0 0
T13 34292 34220 0 0
T18 58244 58175 0 0
T45 24793 24725 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%