Toggle Coverage for Module :
prim_secded_inv_64_57_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T1,*T6,*T12 |
Yes |
T2,T3,T18 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T6,T12,T18 |
Yes |
T1,T3,T6 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T1,T6,T12 |
Yes |
T2,T3,T18 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T6,T18,T44 |
Yes |
T6,T45,T18 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T2,T3,T18 |
Yes |
T6,T18,T44 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
158 |
60.77 |
Total Bits 0->1 |
130 |
79 |
60.77 |
Total Bits 1->0 |
130 |
79 |
60.77 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
158 |
60.77 |
Port Bits 0->1 |
130 |
79 |
60.77 |
Port Bits 1->0 |
130 |
79 |
60.77 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[5:0] |
Yes |
Yes |
*T1,*T6,*T18 |
Yes |
T18,T14,T39 |
INPUT |
data_i[56:6] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T18,T19,T39 |
Yes |
T1,T18,T5 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T1,T6,T18 |
Yes |
T18,T14,T39 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T18,T14,T39 |
Yes |
T18,T14,T59 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T18,T14,T39 |
Yes |
T6,T18,T14 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T8,*T46,*T24 |
Yes |
T36,T8,T46 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T46,T24,T15 |
Yes |
T8,T46,T24 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T8,T46,T24 |
Yes |
T36,T8,T46 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T36,T8,T24 |
Yes |
T8,T46,T15 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T8,T46,T24 |
Yes |
T8,T46,T15 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T6,*T12,*T44 |
Yes |
T2,T3,T6 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T6,T12,T45 |
Yes |
T3,T6,T12 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T6,T12,T44 |
Yes |
T2,T3,T6 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T6,T44,T20 |
Yes |
T6,T45,T44 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T2,T3,T6 |
Yes |
T6,T44,T14 |
OUTPUT |
*Tests covering at least one bit in the range