| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.13 | 96.32 | 90.10 | 92.10 | 94.67 | 90.78 | 98.74 | 61.18 |
| T181 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.144492835 | Aug 23 05:15:07 PM UTC 24 | Aug 23 05:15:13 PM UTC 24 | 2823164613 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2249168136 | Aug 23 05:15:07 PM UTC 24 | Aug 23 05:15:14 PM UTC 24 | 3355512672 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.1318310268 | Aug 23 05:15:08 PM UTC 24 | Aug 23 05:15:14 PM UTC 24 | 4237499541 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3171508318 | Aug 23 05:15:07 PM UTC 24 | Aug 23 05:15:14 PM UTC 24 | 1670534834 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.3902964274 | Aug 23 05:14:15 PM UTC 24 | Aug 23 05:15:16 PM UTC 24 | 9065661742 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1850748103 | Aug 23 05:15:10 PM UTC 24 | Aug 23 05:15:17 PM UTC 24 | 2125909582 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4190177162 | Aug 23 05:14:43 PM UTC 24 | Aug 23 05:15:18 PM UTC 24 | 14244609528 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.567922768 | Aug 23 05:15:11 PM UTC 24 | Aug 23 05:15:21 PM UTC 24 | 8733013327 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.249848553 | Aug 23 05:15:03 PM UTC 24 | Aug 23 05:15:22 PM UTC 24 | 6392410272 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.2625620015 | Aug 23 05:15:02 PM UTC 24 | Aug 23 05:15:23 PM UTC 24 | 13973385726 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1928654405 | Aug 23 05:14:52 PM UTC 24 | Aug 23 05:15:25 PM UTC 24 | 10616615410 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3781405515 | Aug 23 05:13:53 PM UTC 24 | Aug 23 05:15:38 PM UTC 24 | 5415195527 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3441194050 | Aug 23 05:14:33 PM UTC 24 | Aug 23 05:17:26 PM UTC 24 | 60746123703 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1201369673 | Aug 23 05:11:34 PM UTC 24 | Aug 23 05:11:36 PM UTC 24 | 345086079 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.34782478 | Aug 23 05:11:34 PM UTC 24 | Aug 23 05:11:36 PM UTC 24 | 892188344 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2439543586 | Aug 23 05:11:35 PM UTC 24 | Aug 23 05:11:37 PM UTC 24 | 841693026 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2213515127 | Aug 23 05:11:36 PM UTC 24 | Aug 23 05:11:38 PM UTC 24 | 72058071 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3504832676 | Aug 23 05:11:36 PM UTC 24 | Aug 23 05:11:38 PM UTC 24 | 115798627 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1490232975 | Aug 23 05:11:35 PM UTC 24 | Aug 23 05:11:39 PM UTC 24 | 1716292307 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.186338087 | Aug 23 05:11:36 PM UTC 24 | Aug 23 05:11:39 PM UTC 24 | 95322132 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4048471174 | Aug 23 05:11:35 PM UTC 24 | Aug 23 05:11:40 PM UTC 24 | 2106302029 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1071296655 | Aug 23 05:11:37 PM UTC 24 | Aug 23 05:11:40 PM UTC 24 | 143174550 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2520327505 | Aug 23 05:11:37 PM UTC 24 | Aug 23 05:11:40 PM UTC 24 | 104335011 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3048236332 | Aug 23 05:11:38 PM UTC 24 | Aug 23 05:11:41 PM UTC 24 | 359678870 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.343499826 | Aug 23 05:11:37 PM UTC 24 | Aug 23 05:11:42 PM UTC 24 | 117429331 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3818300523 | Aug 23 05:11:36 PM UTC 24 | Aug 23 05:11:42 PM UTC 24 | 541065716 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2599687014 | Aug 23 05:11:39 PM UTC 24 | Aug 23 05:11:42 PM UTC 24 | 282353043 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1903730899 | Aug 23 05:11:41 PM UTC 24 | Aug 23 05:11:43 PM UTC 24 | 1130208639 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2370266801 | Aug 23 05:11:35 PM UTC 24 | Aug 23 05:11:43 PM UTC 24 | 11430090432 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2262875759 | Aug 23 05:11:44 PM UTC 24 | Aug 23 05:11:46 PM UTC 24 | 62363012 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1183544370 | Aug 23 05:11:44 PM UTC 24 | Aug 23 05:11:46 PM UTC 24 | 156322344 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3076555197 | Aug 23 05:11:36 PM UTC 24 | Aug 23 05:11:47 PM UTC 24 | 2678155029 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.3258687687 | Aug 23 05:11:43 PM UTC 24 | Aug 23 05:11:47 PM UTC 24 | 313080401 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2631874188 | Aug 23 05:11:44 PM UTC 24 | Aug 23 05:11:47 PM UTC 24 | 264754619 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3401667095 | Aug 23 05:11:41 PM UTC 24 | Aug 23 05:11:48 PM UTC 24 | 6027956433 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1880619592 | Aug 23 05:11:34 PM UTC 24 | Aug 23 05:11:48 PM UTC 24 | 4912555488 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3512521207 | Aug 23 05:11:45 PM UTC 24 | Aug 23 05:11:48 PM UTC 24 | 103471705 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.568461445 | Aug 23 05:11:40 PM UTC 24 | Aug 23 05:11:49 PM UTC 24 | 12616374616 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3233487724 | Aug 23 05:11:48 PM UTC 24 | Aug 23 05:11:50 PM UTC 24 | 272670978 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3781784255 | Aug 23 05:11:47 PM UTC 24 | Aug 23 05:11:50 PM UTC 24 | 100338992 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1515859092 | Aug 23 05:11:48 PM UTC 24 | Aug 23 05:11:50 PM UTC 24 | 228101672 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2524356396 | Aug 23 05:11:48 PM UTC 24 | Aug 23 05:11:50 PM UTC 24 | 611722229 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.693400355 | Aug 23 05:11:41 PM UTC 24 | Aug 23 05:11:53 PM UTC 24 | 6924543886 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2170903361 | Aug 23 05:11:43 PM UTC 24 | Aug 23 05:11:53 PM UTC 24 | 2860021313 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.575551960 | Aug 23 05:11:49 PM UTC 24 | Aug 23 05:11:54 PM UTC 24 | 4728398412 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2182557437 | Aug 23 05:11:49 PM UTC 24 | Aug 23 05:11:54 PM UTC 24 | 4450312878 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3095474119 | Aug 23 05:11:54 PM UTC 24 | Aug 23 05:11:55 PM UTC 24 | 36213866 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2413566555 | Aug 23 05:11:47 PM UTC 24 | Aug 23 05:11:56 PM UTC 24 | 657248384 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.4130087029 | Aug 23 05:11:51 PM UTC 24 | Aug 23 05:11:56 PM UTC 24 | 169776843 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3293452549 | Aug 23 05:11:35 PM UTC 24 | Aug 23 05:11:56 PM UTC 24 | 37555428075 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.117178342 | Aug 23 05:11:55 PM UTC 24 | Aug 23 05:11:56 PM UTC 24 | 148714162 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1723047599 | Aug 23 05:11:55 PM UTC 24 | Aug 23 05:11:58 PM UTC 24 | 180472763 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2974855485 | Aug 23 05:11:55 PM UTC 24 | Aug 23 05:11:58 PM UTC 24 | 130469420 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2333874490 | Aug 23 05:11:57 PM UTC 24 | Aug 23 05:11:59 PM UTC 24 | 624544549 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1864559953 | Aug 23 05:11:57 PM UTC 24 | Aug 23 05:11:59 PM UTC 24 | 274401410 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2727649789 | Aug 23 05:11:58 PM UTC 24 | Aug 23 05:12:01 PM UTC 24 | 582111511 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2223252482 | Aug 23 05:11:57 PM UTC 24 | Aug 23 05:12:01 PM UTC 24 | 222540706 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1341434300 | Aug 23 05:11:58 PM UTC 24 | Aug 23 05:12:02 PM UTC 24 | 2296692632 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3282418919 | Aug 23 05:11:59 PM UTC 24 | Aug 23 05:12:02 PM UTC 24 | 1620503916 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3676713886 | Aug 23 05:11:48 PM UTC 24 | Aug 23 05:12:04 PM UTC 24 | 16772474689 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.290147896 | Aug 23 05:11:54 PM UTC 24 | Aug 23 05:12:04 PM UTC 24 | 1025807293 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3636909396 | Aug 23 05:11:41 PM UTC 24 | Aug 23 05:12:05 PM UTC 24 | 8486647158 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4063395800 | Aug 23 05:11:43 PM UTC 24 | Aug 23 05:12:05 PM UTC 24 | 7453288669 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.90189121 | Aug 23 05:11:57 PM UTC 24 | Aug 23 05:12:05 PM UTC 24 | 637678000 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.225175279 | Aug 23 05:12:06 PM UTC 24 | Aug 23 05:12:08 PM UTC 24 | 79416216 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2826487535 | Aug 23 05:12:06 PM UTC 24 | Aug 23 05:12:08 PM UTC 24 | 138065214 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1442311846 | Aug 23 05:11:37 PM UTC 24 | Aug 23 05:12:08 PM UTC 24 | 16566348382 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.3447069414 | Aug 23 05:12:03 PM UTC 24 | Aug 23 05:12:08 PM UTC 24 | 308379926 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1018201260 | Aug 23 05:12:06 PM UTC 24 | Aug 23 05:12:08 PM UTC 24 | 122630200 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1069953584 | Aug 23 05:11:34 PM UTC 24 | Aug 23 05:12:09 PM UTC 24 | 10960947725 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.444075266 | Aug 23 05:12:06 PM UTC 24 | Aug 23 05:12:09 PM UTC 24 | 164793170 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2593676364 | Aug 23 05:11:47 PM UTC 24 | Aug 23 05:12:11 PM UTC 24 | 2837426354 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4117593944 | Aug 23 05:12:00 PM UTC 24 | Aug 23 05:12:11 PM UTC 24 | 2812342103 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4172855778 | Aug 23 05:12:09 PM UTC 24 | Aug 23 05:12:11 PM UTC 24 | 208002781 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3750170725 | Aug 23 05:12:09 PM UTC 24 | Aug 23 05:12:11 PM UTC 24 | 461184590 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2585214180 | Aug 23 05:12:09 PM UTC 24 | Aug 23 05:12:12 PM UTC 24 | 259475694 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4090522267 | Aug 23 05:12:10 PM UTC 24 | Aug 23 05:12:12 PM UTC 24 | 204617927 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.639709539 | Aug 23 05:12:09 PM UTC 24 | Aug 23 05:12:14 PM UTC 24 | 1675486702 ps | ||
| T369 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1875819758 | Aug 23 05:12:11 PM UTC 24 | Aug 23 05:12:16 PM UTC 24 | 3102232396 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1961112296 | Aug 23 05:12:13 PM UTC 24 | Aug 23 05:12:18 PM UTC 24 | 182361732 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2149723045 | Aug 23 05:11:46 PM UTC 24 | Aug 23 05:12:21 PM UTC 24 | 3712856677 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2204977700 | Aug 23 05:12:04 PM UTC 24 | Aug 23 05:12:23 PM UTC 24 | 4102521153 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2626197830 | Aug 23 05:12:22 PM UTC 24 | Aug 23 05:12:24 PM UTC 24 | 43748445 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.3996650265 | Aug 23 05:12:22 PM UTC 24 | Aug 23 05:12:24 PM UTC 24 | 144112144 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2430679028 | Aug 23 05:12:09 PM UTC 24 | Aug 23 05:12:34 PM UTC 24 | 634305271 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1673178989 | Aug 23 05:12:23 PM UTC 24 | Aug 23 05:12:26 PM UTC 24 | 92772059 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1326822270 | Aug 23 05:12:23 PM UTC 24 | Aug 23 05:12:26 PM UTC 24 | 152039733 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3817053682 | Aug 23 05:12:24 PM UTC 24 | Aug 23 05:12:26 PM UTC 24 | 610097663 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3005154880 | Aug 23 05:12:23 PM UTC 24 | Aug 23 05:12:28 PM UTC 24 | 1001180854 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2445185558 | Aug 23 05:12:24 PM UTC 24 | Aug 23 05:12:29 PM UTC 24 | 174113553 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1049278984 | Aug 23 05:12:02 PM UTC 24 | Aug 23 05:12:32 PM UTC 24 | 32773044742 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.4215527828 | Aug 23 05:12:30 PM UTC 24 | Aug 23 05:12:36 PM UTC 24 | 365896239 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.382101115 | Aug 23 05:12:11 PM UTC 24 | Aug 23 05:12:33 PM UTC 24 | 7223999495 ps | ||
| T378 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1171545817 | Aug 23 05:11:51 PM UTC 24 | Aug 23 05:12:34 PM UTC 24 | 4511189618 ps | ||
| T379 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1931830362 | Aug 23 05:12:27 PM UTC 24 | Aug 23 05:12:34 PM UTC 24 | 2251586730 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2636945506 | Aug 23 05:11:36 PM UTC 24 | Aug 23 05:12:34 PM UTC 24 | 8213397031 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1251728164 | Aug 23 05:12:33 PM UTC 24 | Aug 23 05:12:36 PM UTC 24 | 424028744 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2777956940 | Aug 23 05:12:35 PM UTC 24 | Aug 23 05:12:37 PM UTC 24 | 941592373 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2782020295 | Aug 23 05:12:34 PM UTC 24 | Aug 23 05:12:38 PM UTC 24 | 192740236 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3397203816 | Aug 23 05:12:35 PM UTC 24 | Aug 23 05:12:39 PM UTC 24 | 130676632 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2554599798 | Aug 23 05:12:37 PM UTC 24 | Aug 23 05:12:40 PM UTC 24 | 108042805 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1998297157 | Aug 23 05:12:15 PM UTC 24 | Aug 23 05:12:41 PM UTC 24 | 7499481731 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1042919042 | Aug 23 05:12:38 PM UTC 24 | Aug 23 05:12:41 PM UTC 24 | 221595826 ps | ||
| T384 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3430281416 | Aug 23 05:12:02 PM UTC 24 | Aug 23 05:12:42 PM UTC 24 | 43793138585 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1864735059 | Aug 23 05:12:35 PM UTC 24 | Aug 23 05:12:44 PM UTC 24 | 7329052407 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.249058746 | Aug 23 05:12:39 PM UTC 24 | Aug 23 05:12:44 PM UTC 24 | 1045817786 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1376487297 | Aug 23 05:11:37 PM UTC 24 | Aug 23 05:12:44 PM UTC 24 | 31703747574 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.244052176 | Aug 23 05:12:39 PM UTC 24 | Aug 23 05:12:44 PM UTC 24 | 225312098 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.302145889 | Aug 23 05:12:12 PM UTC 24 | Aug 23 05:12:45 PM UTC 24 | 3300418484 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2224088025 | Aug 23 05:12:10 PM UTC 24 | Aug 23 05:12:45 PM UTC 24 | 25826722593 ps | ||
| T220 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1578197324 | Aug 23 05:12:37 PM UTC 24 | Aug 23 05:12:47 PM UTC 24 | 2048542578 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.4244649669 | Aug 23 05:12:45 PM UTC 24 | Aug 23 05:12:47 PM UTC 24 | 80980298 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3725457357 | Aug 23 05:12:39 PM UTC 24 | Aug 23 05:12:47 PM UTC 24 | 1710988771 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1336491931 | Aug 23 05:12:43 PM UTC 24 | Aug 23 05:12:48 PM UTC 24 | 168876264 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1455363174 | Aug 23 05:12:46 PM UTC 24 | Aug 23 05:12:48 PM UTC 24 | 668558304 ps | ||
| T218 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3586473211 | Aug 23 05:12:30 PM UTC 24 | Aug 23 05:12:48 PM UTC 24 | 5213671497 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2707544409 | Aug 23 05:12:45 PM UTC 24 | Aug 23 05:12:49 PM UTC 24 | 312606276 ps | ||
| T393 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1993689650 | Aug 23 05:12:26 PM UTC 24 | Aug 23 05:12:51 PM UTC 24 | 15156895947 ps | ||
| T394 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3293948004 | Aug 23 05:12:46 PM UTC 24 | Aug 23 05:12:51 PM UTC 24 | 5264588173 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2588505823 | Aug 23 05:12:49 PM UTC 24 | Aug 23 05:12:52 PM UTC 24 | 135467301 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3011894572 | Aug 23 05:12:49 PM UTC 24 | Aug 23 05:12:53 PM UTC 24 | 96016256 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1140333946 | Aug 23 05:12:48 PM UTC 24 | Aug 23 05:12:53 PM UTC 24 | 175848347 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2256637674 | Aug 23 05:12:45 PM UTC 24 | Aug 23 05:12:53 PM UTC 24 | 734358503 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.355239675 | Aug 23 05:12:52 PM UTC 24 | Aug 23 05:12:54 PM UTC 24 | 168058742 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.686620649 | Aug 23 05:12:41 PM UTC 24 | Aug 23 05:12:54 PM UTC 24 | 4829466079 ps | ||
| T399 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2456943832 | Aug 23 05:12:52 PM UTC 24 | Aug 23 05:12:55 PM UTC 24 | 1583641416 ps | ||
| T400 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1535829146 | Aug 23 05:12:48 PM UTC 24 | Aug 23 05:12:56 PM UTC 24 | 12099408739 ps | ||
| T401 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2492407853 | Aug 23 05:12:52 PM UTC 24 | Aug 23 05:12:56 PM UTC 24 | 3402051637 ps | ||
| T402 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3505074061 | Aug 23 05:12:54 PM UTC 24 | Aug 23 05:12:58 PM UTC 24 | 1604936434 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2838964445 | Aug 23 05:12:49 PM UTC 24 | Aug 23 05:12:58 PM UTC 24 | 3685362801 ps | ||
| T403 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1891214538 | Aug 23 05:12:56 PM UTC 24 | Aug 23 05:12:58 PM UTC 24 | 151035925 ps | ||
| T404 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2636380079 | Aug 23 05:12:48 PM UTC 24 | Aug 23 05:12:58 PM UTC 24 | 3448033677 ps | ||
| T405 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.3296373131 | Aug 23 05:12:53 PM UTC 24 | Aug 23 05:12:59 PM UTC 24 | 301531768 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3616188143 | Aug 23 05:12:45 PM UTC 24 | Aug 23 05:12:59 PM UTC 24 | 2846985701 ps | ||
| T406 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.125773275 | Aug 23 05:12:56 PM UTC 24 | Aug 23 05:13:00 PM UTC 24 | 84771726 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.14800555 | Aug 23 05:12:57 PM UTC 24 | Aug 23 05:13:01 PM UTC 24 | 1106525445 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1187194033 | Aug 23 05:13:03 PM UTC 24 | Aug 23 05:13:20 PM UTC 24 | 6870579208 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.976390520 | Aug 23 05:13:00 PM UTC 24 | Aug 23 05:13:02 PM UTC 24 | 316918776 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3705012785 | Aug 23 05:13:00 PM UTC 24 | Aug 23 05:13:02 PM UTC 24 | 56393929 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2065642962 | Aug 23 05:12:59 PM UTC 24 | Aug 23 05:13:02 PM UTC 24 | 345114549 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2826216022 | Aug 23 05:13:01 PM UTC 24 | Aug 23 05:13:02 PM UTC 24 | 243130522 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3485909565 | Aug 23 05:12:55 PM UTC 24 | Aug 23 05:13:03 PM UTC 24 | 1165435685 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2913264740 | Aug 23 05:12:54 PM UTC 24 | Aug 23 05:13:04 PM UTC 24 | 2134362282 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1028994032 | Aug 23 05:12:28 PM UTC 24 | Aug 23 05:13:04 PM UTC 24 | 1690828812 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3125658771 | Aug 23 05:11:57 PM UTC 24 | Aug 23 05:13:04 PM UTC 24 | 15780396380 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1871876298 | Aug 23 05:13:00 PM UTC 24 | Aug 23 05:13:05 PM UTC 24 | 709153764 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1526504962 | Aug 23 05:11:56 PM UTC 24 | Aug 23 05:13:05 PM UTC 24 | 91256926727 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2232634803 | Aug 23 05:13:03 PM UTC 24 | Aug 23 05:13:06 PM UTC 24 | 129551714 ps | ||
| T415 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.1331051361 | Aug 23 05:13:03 PM UTC 24 | Aug 23 05:13:07 PM UTC 24 | 480786644 ps | ||
| T416 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1341240263 | Aug 23 05:13:05 PM UTC 24 | Aug 23 05:13:07 PM UTC 24 | 201190285 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1687489849 | Aug 23 05:13:03 PM UTC 24 | Aug 23 05:13:08 PM UTC 24 | 256969805 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.989886177 | Aug 23 05:13:05 PM UTC 24 | Aug 23 05:13:08 PM UTC 24 | 155343670 ps | ||
| T417 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2627620183 | Aug 23 05:13:03 PM UTC 24 | Aug 23 05:13:09 PM UTC 24 | 13305860994 ps | ||
| T418 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3634398775 | Aug 23 05:13:01 PM UTC 24 | Aug 23 05:13:09 PM UTC 24 | 7104683665 ps | ||
| T419 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1237639480 | Aug 23 05:13:07 PM UTC 24 | Aug 23 05:13:10 PM UTC 24 | 99125136 ps | ||
| T420 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2028127119 | Aug 23 05:13:08 PM UTC 24 | Aug 23 05:13:11 PM UTC 24 | 372198778 ps | ||
| T421 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1931451310 | Aug 23 05:13:08 PM UTC 24 | Aug 23 05:13:12 PM UTC 24 | 148477374 ps | ||
| T422 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2966041984 | Aug 23 05:13:06 PM UTC 24 | Aug 23 05:13:13 PM UTC 24 | 151412635 ps | ||
| T423 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2705146275 | Aug 23 05:13:05 PM UTC 24 | Aug 23 05:13:13 PM UTC 24 | 2056524578 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.127721933 | Aug 23 05:13:08 PM UTC 24 | Aug 23 05:13:13 PM UTC 24 | 214917463 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4291834335 | Aug 23 05:12:02 PM UTC 24 | Aug 23 05:13:13 PM UTC 24 | 3473180810 ps | ||
| T424 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1792824754 | Aug 23 05:12:07 PM UTC 24 | Aug 23 05:13:14 PM UTC 24 | 38252539566 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.438488403 | Aug 23 05:13:11 PM UTC 24 | Aug 23 05:13:15 PM UTC 24 | 289057622 ps | ||
| T426 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3467379504 | Aug 23 05:13:10 PM UTC 24 | Aug 23 05:13:15 PM UTC 24 | 5769869609 ps | ||
| T427 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.318417791 | Aug 23 05:13:14 PM UTC 24 | Aug 23 05:13:16 PM UTC 24 | 289207445 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.897131742 | Aug 23 05:13:13 PM UTC 24 | Aug 23 05:13:16 PM UTC 24 | 371904515 ps | ||
| T428 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3538596926 | Aug 23 05:13:14 PM UTC 24 | Aug 23 05:13:16 PM UTC 24 | 48933883 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.455903498 | Aug 23 05:11:42 PM UTC 24 | Aug 23 05:13:19 PM UTC 24 | 42438463552 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.123509581 | Aug 23 05:13:14 PM UTC 24 | Aug 23 05:13:19 PM UTC 24 | 2673119248 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.2451148420 | Aug 23 05:13:15 PM UTC 24 | Aug 23 05:13:19 PM UTC 24 | 245740327 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3556339005 | Aug 23 05:13:16 PM UTC 24 | Aug 23 05:13:19 PM UTC 24 | 59098813 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3043172777 | Aug 23 05:12:59 PM UTC 24 | Aug 23 05:13:19 PM UTC 24 | 8280969100 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2132312905 | Aug 23 05:13:17 PM UTC 24 | Aug 23 05:13:21 PM UTC 24 | 202845124 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.746376412 | Aug 23 05:13:19 PM UTC 24 | Aug 23 05:13:21 PM UTC 24 | 52016019 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2228526331 | Aug 23 05:13:17 PM UTC 24 | Aug 23 05:13:21 PM UTC 24 | 208116201 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3891941314 | Aug 23 05:13:19 PM UTC 24 | Aug 23 05:13:21 PM UTC 24 | 398243626 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4227942953 | Aug 23 05:13:14 PM UTC 24 | Aug 23 05:13:22 PM UTC 24 | 300264789 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3211281150 | Aug 23 05:12:35 PM UTC 24 | Aug 23 05:13:22 PM UTC 24 | 19143964983 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4201811853 | Aug 23 05:11:50 PM UTC 24 | Aug 23 05:13:23 PM UTC 24 | 71522297306 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1876220855 | Aug 23 05:13:21 PM UTC 24 | Aug 23 05:13:24 PM UTC 24 | 149781757 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2145424238 | Aug 23 05:13:20 PM UTC 24 | Aug 23 05:13:24 PM UTC 24 | 164267506 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3803800841 | Aug 23 05:12:23 PM UTC 24 | Aug 23 05:13:24 PM UTC 24 | 19513956237 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1941508481 | Aug 23 05:13:21 PM UTC 24 | Aug 23 05:13:25 PM UTC 24 | 114059368 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1841840547 | Aug 23 05:11:50 PM UTC 24 | Aug 23 05:13:25 PM UTC 24 | 55933676630 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1217273382 | Aug 23 05:13:22 PM UTC 24 | Aug 23 05:13:25 PM UTC 24 | 1937887772 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3720605856 | Aug 23 05:12:59 PM UTC 24 | Aug 23 05:13:25 PM UTC 24 | 17835319498 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3354957985 | Aug 23 05:13:06 PM UTC 24 | Aug 23 05:13:25 PM UTC 24 | 1700223008 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1188530090 | Aug 23 05:13:15 PM UTC 24 | Aug 23 05:13:26 PM UTC 24 | 6795572333 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.708076805 | Aug 23 05:12:35 PM UTC 24 | Aug 23 05:13:26 PM UTC 24 | 4568781498 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.200269105 | Aug 23 05:13:21 PM UTC 24 | Aug 23 05:13:26 PM UTC 24 | 1097116053 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1550142858 | Aug 23 05:13:05 PM UTC 24 | Aug 23 05:13:27 PM UTC 24 | 25576673429 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2443641725 | Aug 23 05:13:22 PM UTC 24 | Aug 23 05:13:27 PM UTC 24 | 853608646 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.349535326 | Aug 23 05:13:16 PM UTC 24 | Aug 23 05:13:27 PM UTC 24 | 1187265640 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.2439756047 | Aug 23 05:13:25 PM UTC 24 | Aug 23 05:13:27 PM UTC 24 | 109801755 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1925339000 | Aug 23 05:13:25 PM UTC 24 | Aug 23 05:13:27 PM UTC 24 | 302523711 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.2854956273 | Aug 23 05:13:24 PM UTC 24 | Aug 23 05:13:28 PM UTC 24 | 520582013 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2088197349 | Aug 23 05:13:26 PM UTC 24 | Aug 23 05:13:28 PM UTC 24 | 284563848 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.818222120 | Aug 23 05:13:25 PM UTC 24 | Aug 23 05:13:29 PM UTC 24 | 212450119 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3834050039 | Aug 23 05:13:27 PM UTC 24 | Aug 23 05:13:30 PM UTC 24 | 351091323 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3384171701 | Aug 23 05:13:20 PM UTC 24 | Aug 23 05:13:31 PM UTC 24 | 3179698331 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3057218426 | Aug 23 05:13:28 PM UTC 24 | Aug 23 05:13:31 PM UTC 24 | 149668586 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.2077823614 | Aug 23 05:13:26 PM UTC 24 | Aug 23 05:13:31 PM UTC 24 | 269711613 ps | ||
| T222 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1704309550 | Aug 23 05:13:24 PM UTC 24 | Aug 23 05:13:32 PM UTC 24 | 1191521805 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3015599285 | Aug 23 05:12:48 PM UTC 24 | Aug 23 05:13:32 PM UTC 24 | 3073706004 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3357676700 | Aug 23 05:13:19 PM UTC 24 | Aug 23 05:13:32 PM UTC 24 | 5947501846 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1701785231 | Aug 23 05:13:29 PM UTC 24 | Aug 23 05:13:32 PM UTC 24 | 74176684 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.745648026 | Aug 23 05:13:27 PM UTC 24 | Aug 23 05:13:32 PM UTC 24 | 84534211 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1870109012 | Aug 23 05:13:27 PM UTC 24 | Aug 23 05:13:33 PM UTC 24 | 622991743 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.665003876 | Aug 23 05:13:28 PM UTC 24 | Aug 23 05:13:34 PM UTC 24 | 150499667 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1686837931 | Aug 23 05:13:26 PM UTC 24 | Aug 23 05:13:34 PM UTC 24 | 4055445183 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3498744714 | Aug 23 05:13:31 PM UTC 24 | Aug 23 05:13:34 PM UTC 24 | 414859831 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3189712577 | Aug 23 05:13:29 PM UTC 24 | Aug 23 05:13:35 PM UTC 24 | 350693110 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3791025230 | Aug 23 05:13:30 PM UTC 24 | Aug 23 05:13:35 PM UTC 24 | 89448827 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2409679417 | Aug 23 05:13:28 PM UTC 24 | Aug 23 05:13:35 PM UTC 24 | 3318487031 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1486674508 | Aug 23 05:13:33 PM UTC 24 | Aug 23 05:13:35 PM UTC 24 | 239270664 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.568663905 | Aug 23 05:13:31 PM UTC 24 | Aug 23 05:13:36 PM UTC 24 | 2558779163 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1374287764 | Aug 23 05:13:34 PM UTC 24 | Aug 23 05:13:37 PM UTC 24 | 132768887 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3236262542 | Aug 23 05:13:31 PM UTC 24 | Aug 23 05:13:37 PM UTC 24 | 1552340265 ps | ||
| T219 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3748485722 | Aug 23 05:13:12 PM UTC 24 | Aug 23 05:13:38 PM UTC 24 | 7005606365 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1754246447 | Aug 23 05:13:31 PM UTC 24 | Aug 23 05:13:38 PM UTC 24 | 2269086370 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1724641886 | Aug 23 05:13:26 PM UTC 24 | Aug 23 05:13:38 PM UTC 24 | 17762118739 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1527137005 | Aug 23 05:13:33 PM UTC 24 | Aug 23 05:13:40 PM UTC 24 | 378816390 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.677337121 | Aug 23 05:13:28 PM UTC 24 | Aug 23 05:13:44 PM UTC 24 | 1766678973 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1639286580 | Aug 23 05:13:32 PM UTC 24 | Aug 23 05:13:44 PM UTC 24 | 1303851972 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3363152569 | Aug 23 05:12:53 PM UTC 24 | Aug 23 05:13:45 PM UTC 24 | 4962768401 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1095089072 | Aug 23 05:12:42 PM UTC 24 | Aug 23 05:13:54 PM UTC 24 | 25470815650 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4106214083 | Aug 23 05:13:26 PM UTC 24 | Aug 23 05:13:54 PM UTC 24 | 5200174064 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3910274838 | Aug 23 05:13:28 PM UTC 24 | Aug 23 05:13:55 PM UTC 24 | 15799493709 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.206207791 | Aug 23 05:12:12 PM UTC 24 | Aug 23 05:13:57 PM UTC 24 | 48493476172 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1724299111 | Aug 23 05:12:43 PM UTC 24 | Aug 23 05:14:02 PM UTC 24 | 21012252833 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3471183056 | Aug 23 05:13:22 PM UTC 24 | Aug 23 05:14:17 PM UTC 24 | 65800866017 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.4055053676 | Aug 23 05:13:10 PM UTC 24 | Aug 23 05:14:57 PM UTC 24 | 38436194910 ps | ||
| T483 | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.643292369 | Aug 23 05:12:12 PM UTC 24 | Aug 23 05:15:49 PM UTC 24 | 87557842567 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3077061184 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1019281192 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 05:13:35 PM UTC 24 |
| Finished | Aug 23 05:13:37 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077061184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3077061184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.204917532 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 886886067 ps |
| CPU time | 22.66 seconds |
| Started | Aug 23 05:14:00 PM UTC 24 |
| Finished | Aug 23 05:14:24 PM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=204917532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress _all_with_rand_reset.204917532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2146063647 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 937113806 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 05:13:39 PM UTC 24 |
| Finished | Aug 23 05:13:42 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146063647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2146063647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4145732152 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7319857977 ps |
| CPU time | 3.86 seconds |
| Started | Aug 23 05:13:43 PM UTC 24 |
| Finished | Aug 23 05:13:48 PM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145732152 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.4145732152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3314365704 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11415825985 ps |
| CPU time | 8.96 seconds |
| Started | Aug 23 05:13:34 PM UTC 24 |
| Finished | Aug 23 05:13:44 PM UTC 24 |
| Peak memory | 216152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314365704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3314365704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.300156872 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11066108043 ps |
| CPU time | 10.3 seconds |
| Started | Aug 23 05:13:51 PM UTC 24 |
| Finished | Aug 23 05:14:03 PM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300156872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.300156872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3076555197 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2678155029 ps |
| CPU time | 9.44 seconds |
| Started | Aug 23 05:11:36 PM UTC 24 |
| Finished | Aug 23 05:11:47 PM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076555197 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3076555197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3781405515 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5415195527 ps |
| CPU time | 103.35 seconds |
| Started | Aug 23 05:13:53 PM UTC 24 |
| Finished | Aug 23 05:15:38 PM UTC 24 |
| Peak memory | 233316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3781405515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.3781405515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2879649011 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 229193335 ps |
| CPU time | 1.31 seconds |
| Started | Aug 23 05:13:49 PM UTC 24 |
| Finished | Aug 23 05:13:52 PM UTC 24 |
| Peak memory | 251996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879649011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.2879649011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1724299111 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 21012252833 ps |
| CPU time | 77.23 seconds |
| Started | Aug 23 05:12:43 PM UTC 24 |
| Finished | Aug 23 05:14:02 PM UTC 24 |
| Peak memory | 232016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1724299111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re set.1724299111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.63265529 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 638403234 ps |
| CPU time | 2.29 seconds |
| Started | Aug 23 05:13:41 PM UTC 24 |
| Finished | Aug 23 05:13:44 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63265529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.63265529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.4125865351 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5076808071 ps |
| CPU time | 65.26 seconds |
| Started | Aug 23 05:14:06 PM UTC 24 |
| Finished | Aug 23 05:15:13 PM UTC 24 |
| Peak memory | 233408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4125865351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stres s_all_with_rand_reset.4125865351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3271429971 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13162178983 ps |
| CPU time | 50.59 seconds |
| Started | Aug 23 05:14:11 PM UTC 24 |
| Finished | Aug 23 05:15:03 PM UTC 24 |
| Peak memory | 233272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3271429971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres s_all_with_rand_reset.3271429971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.626581748 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 30118971 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 05:13:43 PM UTC 24 |
| Finished | Aug 23 05:13:44 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626581748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.626581748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_scanmode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2058990339 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6267504652 ps |
| CPU time | 10.01 seconds |
| Started | Aug 23 05:14:03 PM UTC 24 |
| Finished | Aug 23 05:14:14 PM UTC 24 |
| Peak memory | 226432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058990339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2058990339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1897359304 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 428357334 ps |
| CPU time | 1.42 seconds |
| Started | Aug 23 05:13:51 PM UTC 24 |
| Finished | Aug 23 05:13:54 PM UTC 24 |
| Peak memory | 253436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897359304 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1897359304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3992817678 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10797208100 ps |
| CPU time | 56.72 seconds |
| Started | Aug 23 05:14:04 PM UTC 24 |
| Finished | Aug 23 05:15:02 PM UTC 24 |
| Peak memory | 233236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3992817678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stres s_all_with_rand_reset.3992817678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1159027491 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 353079331 ps |
| CPU time | 1.54 seconds |
| Started | Aug 23 05:13:36 PM UTC 24 |
| Finished | Aug 23 05:13:39 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159027491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1159027491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4063395800 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 7453288669 ps |
| CPU time | 20.57 seconds |
| Started | Aug 23 05:11:43 PM UTC 24 |
| Finished | Aug 23 05:12:05 PM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4063395800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_re set.4063395800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3125658771 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 15780396380 ps |
| CPU time | 65.57 seconds |
| Started | Aug 23 05:11:57 PM UTC 24 |
| Finished | Aug 23 05:13:04 PM UTC 24 |
| Peak memory | 215432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125658771 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.3125658771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2886847246 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 126191928 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 05:13:39 PM UTC 24 |
| Finished | Aug 23 05:13:41 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886847246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2886847246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.3804051963 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 33424902 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:13:43 PM UTC 24 |
| Finished | Aug 23 05:13:45 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804051963 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3804051963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.4140928122 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3253748185 ps |
| CPU time | 8.9 seconds |
| Started | Aug 23 05:14:32 PM UTC 24 |
| Finished | Aug 23 05:14:42 PM UTC 24 |
| Peak memory | 226472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140928122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4140928122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.3902964274 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9065661742 ps |
| CPU time | 59.37 seconds |
| Started | Aug 23 05:14:15 PM UTC 24 |
| Finished | Aug 23 05:15:16 PM UTC 24 |
| Peak memory | 233272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3902964274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres s_all_with_rand_reset.3902964274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1998297157 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 7499481731 ps |
| CPU time | 23.93 seconds |
| Started | Aug 23 05:12:15 PM UTC 24 |
| Finished | Aug 23 05:12:41 PM UTC 24 |
| Peak memory | 232352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998297157 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1998297157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.343499826 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 117429331 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 05:11:37 PM UTC 24 |
| Finished | Aug 23 05:11:42 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343499826 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.343499826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2445522025 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 77176671 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 05:13:40 PM UTC 24 |
| Finished | Aug 23 05:13:42 PM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445522025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2445522025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2002757037 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 363537593 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 05:13:56 PM UTC 24 |
| Finished | Aug 23 05:13:58 PM UTC 24 |
| Peak memory | 257236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002757037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.2002757037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.484113392 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3220347442 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 05:14:56 PM UTC 24 |
| Finished | Aug 23 05:15:01 PM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484113392 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.484113392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.514979896 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 29719512391 ps |
| CPU time | 12.22 seconds |
| Started | Aug 23 05:14:28 PM UTC 24 |
| Finished | Aug 23 05:14:41 PM UTC 24 |
| Peak memory | 226568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514979896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.514979896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3748485722 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 7005606365 ps |
| CPU time | 24.73 seconds |
| Started | Aug 23 05:13:12 PM UTC 24 |
| Finished | Aug 23 05:13:38 PM UTC 24 |
| Peak memory | 232360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748485722 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3748485722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.3501250653 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 650047291 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 05:15:00 PM UTC 24 |
| Finished | Aug 23 05:15:03 PM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501250653 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3501250653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/31.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3012947054 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3342386562 ps |
| CPU time | 2.62 seconds |
| Started | Aug 23 05:15:01 PM UTC 24 |
| Finished | Aug 23 05:15:05 PM UTC 24 |
| Peak memory | 216116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012947054 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3012947054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.1833164334 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2766805415 ps |
| CPU time | 2.47 seconds |
| Started | Aug 23 05:13:46 PM UTC 24 |
| Finished | Aug 23 05:13:50 PM UTC 24 |
| Peak memory | 216088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833164334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1833164334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.575303831 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 7529953485 ps |
| CPU time | 18.13 seconds |
| Started | Aug 23 05:13:50 PM UTC 24 |
| Finished | Aug 23 05:14:10 PM UTC 24 |
| Peak memory | 226328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575303831 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.575303831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2439543586 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 841693026 ps |
| CPU time | 0.8 seconds |
| Started | Aug 23 05:11:35 PM UTC 24 |
| Finished | Aug 23 05:11:37 PM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439543586 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.2439543586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4048471174 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2106302029 ps |
| CPU time | 3.59 seconds |
| Started | Aug 23 05:11:35 PM UTC 24 |
| Finished | Aug 23 05:11:40 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048471174 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.4048471174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3352060927 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 414739354 ps |
| CPU time | 1.63 seconds |
| Started | Aug 23 05:13:38 PM UTC 24 |
| Finished | Aug 23 05:13:41 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352060927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3352060927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2170903361 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2860021313 ps |
| CPU time | 8.76 seconds |
| Started | Aug 23 05:11:43 PM UTC 24 |
| Finished | Aug 23 05:11:53 PM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170903361 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2170903361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1704309550 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1191521805 ps |
| CPU time | 6.95 seconds |
| Started | Aug 23 05:13:24 PM UTC 24 |
| Finished | Aug 23 05:13:32 PM UTC 24 |
| Peak memory | 225296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704309550 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1704309550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4106214083 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5200174064 ps |
| CPU time | 26.59 seconds |
| Started | Aug 23 05:13:26 PM UTC 24 |
| Finished | Aug 23 05:13:54 PM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106214083 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4106214083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2628682644 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2214650255 ps |
| CPU time | 6.69 seconds |
| Started | Aug 23 05:14:39 PM UTC 24 |
| Finished | Aug 23 05:14:47 PM UTC 24 |
| Peak memory | 226496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628682644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2628682644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.774458627 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1603870939 ps |
| CPU time | 2.05 seconds |
| Started | Aug 23 05:14:40 PM UTC 24 |
| Finished | Aug 23 05:14:43 PM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774458627 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.774458627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.4244649669 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 80980298 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 05:12:45 PM UTC 24 |
| Finished | Aug 23 05:12:47 PM UTC 24 |
| Peak memory | 229168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244649669 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4244649669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.363057983 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 99077888 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 05:13:43 PM UTC 24 |
| Finished | Aug 23 05:13:45 PM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363057983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.363057983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1706039454 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 139100305 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 05:13:50 PM UTC 24 |
| Finished | Aug 23 05:13:52 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706039454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.1706039454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4151702554 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 204165147 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:13:40 PM UTC 24 |
| Finished | Aug 23 05:13:42 PM UTC 24 |
| Peak memory | 213104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151702554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4151702554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1069953584 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 10960947725 ps |
| CPU time | 33.48 seconds |
| Started | Aug 23 05:11:34 PM UTC 24 |
| Finished | Aug 23 05:12:09 PM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069953584 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.1069953584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1376487297 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 31703747574 ps |
| CPU time | 64.98 seconds |
| Started | Aug 23 05:11:37 PM UTC 24 |
| Finished | Aug 23 05:12:44 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376487297 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1376487297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.186338087 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 95322132 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 05:11:36 PM UTC 24 |
| Finished | Aug 23 05:11:39 PM UTC 24 |
| Peak memory | 225288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186338087 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.186338087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2520327505 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 104335011 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 05:11:37 PM UTC 24 |
| Finished | Aug 23 05:11:40 PM UTC 24 |
| Peak memory | 227188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2520327505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_r and_reset.2520327505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1071296655 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 143174550 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 05:11:37 PM UTC 24 |
| Finished | Aug 23 05:11:40 PM UTC 24 |
| Peak memory | 225168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071296655 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1071296655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3293452549 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 37555428075 ps |
| CPU time | 19.89 seconds |
| Started | Aug 23 05:11:35 PM UTC 24 |
| Finished | Aug 23 05:11:56 PM UTC 24 |
| Peak memory | 215476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293452549 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.3293452549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2370266801 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 11430090432 ps |
| CPU time | 7.4 seconds |
| Started | Aug 23 05:11:35 PM UTC 24 |
| Finished | Aug 23 05:11:43 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370266801 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.2370266801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1490232975 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1716292307 ps |
| CPU time | 2.96 seconds |
| Started | Aug 23 05:11:35 PM UTC 24 |
| Finished | Aug 23 05:11:39 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490232975 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1490232975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1880619592 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4912555488 ps |
| CPU time | 12.59 seconds |
| Started | Aug 23 05:11:34 PM UTC 24 |
| Finished | Aug 23 05:11:48 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880619592 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.1880619592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1201369673 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 345086079 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 05:11:34 PM UTC 24 |
| Finished | Aug 23 05:11:36 PM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201369673 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.1201369673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.34782478 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 892188344 ps |
| CPU time | 1.66 seconds |
| Started | Aug 23 05:11:34 PM UTC 24 |
| Finished | Aug 23 05:11:36 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34782478 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.34782478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2213515127 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 72058071 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 05:11:36 PM UTC 24 |
| Finished | Aug 23 05:11:38 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213515127 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.2213515127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3504832676 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 115798627 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 05:11:36 PM UTC 24 |
| Finished | Aug 23 05:11:38 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504832676 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3504832676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2636945506 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 8213397031 ps |
| CPU time | 56.69 seconds |
| Started | Aug 23 05:11:36 PM UTC 24 |
| Finished | Aug 23 05:12:34 PM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2636945506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re set.2636945506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3818300523 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 541065716 ps |
| CPU time | 4.72 seconds |
| Started | Aug 23 05:11:36 PM UTC 24 |
| Finished | Aug 23 05:11:42 PM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818300523 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3818300523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1442311846 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 16566348382 ps |
| CPU time | 29.25 seconds |
| Started | Aug 23 05:11:37 PM UTC 24 |
| Finished | Aug 23 05:12:08 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442311846 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.1442311846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2149723045 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3712856677 ps |
| CPU time | 33.17 seconds |
| Started | Aug 23 05:11:46 PM UTC 24 |
| Finished | Aug 23 05:12:21 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149723045 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2149723045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2631874188 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 264754619 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 05:11:44 PM UTC 24 |
| Finished | Aug 23 05:11:47 PM UTC 24 |
| Peak memory | 225164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631874188 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2631874188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3781784255 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 100338992 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 05:11:47 PM UTC 24 |
| Finished | Aug 23 05:11:50 PM UTC 24 |
| Peak memory | 229236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3781784255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r and_reset.3781784255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3512521207 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 103471705 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 05:11:45 PM UTC 24 |
| Finished | Aug 23 05:11:48 PM UTC 24 |
| Peak memory | 225296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512521207 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3512521207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.455903498 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 42438463552 ps |
| CPU time | 95.01 seconds |
| Started | Aug 23 05:11:42 PM UTC 24 |
| Finished | Aug 23 05:13:19 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455903498 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.455903498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3401667095 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 6027956433 ps |
| CPU time | 5.7 seconds |
| Started | Aug 23 05:11:41 PM UTC 24 |
| Finished | Aug 23 05:11:48 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401667095 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.3401667095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3636909396 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 8486647158 ps |
| CPU time | 22.99 seconds |
| Started | Aug 23 05:11:41 PM UTC 24 |
| Finished | Aug 23 05:12:05 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636909396 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.3636909396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.693400355 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 6924543886 ps |
| CPU time | 10.68 seconds |
| Started | Aug 23 05:11:41 PM UTC 24 |
| Finished | Aug 23 05:11:53 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693400355 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.693400355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1903730899 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1130208639 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 05:11:41 PM UTC 24 |
| Finished | Aug 23 05:11:43 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903730899 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.1903730899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.568461445 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 12616374616 ps |
| CPU time | 7.04 seconds |
| Started | Aug 23 05:11:40 PM UTC 24 |
| Finished | Aug 23 05:11:49 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568461445 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.568461445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3048236332 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 359678870 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 05:11:38 PM UTC 24 |
| Finished | Aug 23 05:11:41 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048236332 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.3048236332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2599687014 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 282353043 ps |
| CPU time | 1.31 seconds |
| Started | Aug 23 05:11:39 PM UTC 24 |
| Finished | Aug 23 05:11:42 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599687014 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2599687014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2262875759 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 62363012 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 05:11:44 PM UTC 24 |
| Finished | Aug 23 05:11:46 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262875759 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.2262875759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1183544370 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 156322344 ps |
| CPU time | 0.8 seconds |
| Started | Aug 23 05:11:44 PM UTC 24 |
| Finished | Aug 23 05:11:46 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183544370 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1183544370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2413566555 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 657248384 ps |
| CPU time | 7.36 seconds |
| Started | Aug 23 05:11:47 PM UTC 24 |
| Finished | Aug 23 05:11:56 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413566555 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.2413566555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.3258687687 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 313080401 ps |
| CPU time | 2.88 seconds |
| Started | Aug 23 05:11:43 PM UTC 24 |
| Finished | Aug 23 05:11:47 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258687687 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3258687687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3705012785 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 56393929 ps |
| CPU time | 1.57 seconds |
| Started | Aug 23 05:13:00 PM UTC 24 |
| Finished | Aug 23 05:13:02 PM UTC 24 |
| Peak memory | 227156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3705012785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_ rand_reset.3705012785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.976390520 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 316918776 ps |
| CPU time | 1.39 seconds |
| Started | Aug 23 05:13:00 PM UTC 24 |
| Finished | Aug 23 05:13:02 PM UTC 24 |
| Peak memory | 225196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976390520 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.976390520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3720605856 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 17835319498 ps |
| CPU time | 25.55 seconds |
| Started | Aug 23 05:12:59 PM UTC 24 |
| Finished | Aug 23 05:13:25 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720605856 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.3720605856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.14800555 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1106525445 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 05:12:57 PM UTC 24 |
| Finished | Aug 23 05:13:01 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14800555 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.14800555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1891214538 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 151035925 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 05:12:56 PM UTC 24 |
| Finished | Aug 23 05:12:58 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891214538 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1891214538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1871876298 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 709153764 ps |
| CPU time | 4.01 seconds |
| Started | Aug 23 05:13:00 PM UTC 24 |
| Finished | Aug 23 05:13:05 PM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871876298 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.1871876298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2065642962 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 345114549 ps |
| CPU time | 2.75 seconds |
| Started | Aug 23 05:12:59 PM UTC 24 |
| Finished | Aug 23 05:13:02 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065642962 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2065642962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3043172777 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 8280969100 ps |
| CPU time | 19.48 seconds |
| Started | Aug 23 05:12:59 PM UTC 24 |
| Finished | Aug 23 05:13:19 PM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043172777 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3043172777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.989886177 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 155343670 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 05:13:05 PM UTC 24 |
| Finished | Aug 23 05:13:08 PM UTC 24 |
| Peak memory | 225116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=989886177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_r and_reset.989886177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2232634803 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 129551714 ps |
| CPU time | 1.43 seconds |
| Started | Aug 23 05:13:03 PM UTC 24 |
| Finished | Aug 23 05:13:06 PM UTC 24 |
| Peak memory | 225228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232634803 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2232634803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2627620183 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 13305860994 ps |
| CPU time | 4.57 seconds |
| Started | Aug 23 05:13:03 PM UTC 24 |
| Finished | Aug 23 05:13:09 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627620183 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.2627620183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3634398775 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 7104683665 ps |
| CPU time | 7.3 seconds |
| Started | Aug 23 05:13:01 PM UTC 24 |
| Finished | Aug 23 05:13:09 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634398775 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.3634398775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2826216022 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 243130522 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 05:13:01 PM UTC 24 |
| Finished | Aug 23 05:13:02 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826216022 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.2826216022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1687489849 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 256969805 ps |
| CPU time | 3.91 seconds |
| Started | Aug 23 05:13:03 PM UTC 24 |
| Finished | Aug 23 05:13:08 PM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687489849 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.1687489849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.1331051361 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 480786644 ps |
| CPU time | 2.63 seconds |
| Started | Aug 23 05:13:03 PM UTC 24 |
| Finished | Aug 23 05:13:07 PM UTC 24 |
| Peak memory | 225916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331051361 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1331051361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1187194033 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 6870579208 ps |
| CPU time | 16.16 seconds |
| Started | Aug 23 05:13:03 PM UTC 24 |
| Finished | Aug 23 05:13:20 PM UTC 24 |
| Peak memory | 227824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187194033 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1187194033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1931451310 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 148477374 ps |
| CPU time | 2.72 seconds |
| Started | Aug 23 05:13:08 PM UTC 24 |
| Finished | Aug 23 05:13:12 PM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1931451310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_ rand_reset.1931451310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1237639480 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 99125136 ps |
| CPU time | 1.16 seconds |
| Started | Aug 23 05:13:07 PM UTC 24 |
| Finished | Aug 23 05:13:10 PM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237639480 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1237639480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1550142858 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 25576673429 ps |
| CPU time | 20.27 seconds |
| Started | Aug 23 05:13:05 PM UTC 24 |
| Finished | Aug 23 05:13:27 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550142858 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.1550142858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2705146275 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2056524578 ps |
| CPU time | 6.51 seconds |
| Started | Aug 23 05:13:05 PM UTC 24 |
| Finished | Aug 23 05:13:13 PM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705146275 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.2705146275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1341240263 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 201190285 ps |
| CPU time | 1.14 seconds |
| Started | Aug 23 05:13:05 PM UTC 24 |
| Finished | Aug 23 05:13:07 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341240263 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.1341240263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.127721933 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 214917463 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 05:13:08 PM UTC 24 |
| Finished | Aug 23 05:13:13 PM UTC 24 |
| Peak memory | 215440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127721933 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.127721933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.2966041984 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 151412635 ps |
| CPU time | 5.19 seconds |
| Started | Aug 23 05:13:06 PM UTC 24 |
| Finished | Aug 23 05:13:13 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966041984 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2966041984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3354957985 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1700223008 ps |
| CPU time | 17.73 seconds |
| Started | Aug 23 05:13:06 PM UTC 24 |
| Finished | Aug 23 05:13:25 PM UTC 24 |
| Peak memory | 232432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354957985 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3354957985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3538596926 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 48933883 ps |
| CPU time | 1.52 seconds |
| Started | Aug 23 05:13:14 PM UTC 24 |
| Finished | Aug 23 05:13:16 PM UTC 24 |
| Peak memory | 227188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3538596926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_ rand_reset.3538596926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.897131742 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 371904515 ps |
| CPU time | 2.11 seconds |
| Started | Aug 23 05:13:13 PM UTC 24 |
| Finished | Aug 23 05:13:16 PM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897131742 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.897131742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.4055053676 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 38436194910 ps |
| CPU time | 105.93 seconds |
| Started | Aug 23 05:13:10 PM UTC 24 |
| Finished | Aug 23 05:14:57 PM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055053676 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.4055053676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3467379504 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 5769869609 ps |
| CPU time | 4.68 seconds |
| Started | Aug 23 05:13:10 PM UTC 24 |
| Finished | Aug 23 05:13:15 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467379504 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.3467379504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2028127119 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 372198778 ps |
| CPU time | 1.47 seconds |
| Started | Aug 23 05:13:08 PM UTC 24 |
| Finished | Aug 23 05:13:11 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028127119 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.2028127119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4227942953 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 300264789 ps |
| CPU time | 6.93 seconds |
| Started | Aug 23 05:13:14 PM UTC 24 |
| Finished | Aug 23 05:13:22 PM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227942953 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.4227942953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.438488403 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 289057622 ps |
| CPU time | 2.89 seconds |
| Started | Aug 23 05:13:11 PM UTC 24 |
| Finished | Aug 23 05:13:15 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438488403 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.438488403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2132312905 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 202845124 ps |
| CPU time | 2.55 seconds |
| Started | Aug 23 05:13:17 PM UTC 24 |
| Finished | Aug 23 05:13:21 PM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2132312905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.2132312905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3556339005 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 59098813 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 05:13:16 PM UTC 24 |
| Finished | Aug 23 05:13:19 PM UTC 24 |
| Peak memory | 231212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556339005 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3556339005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1188530090 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 6795572333 ps |
| CPU time | 9.47 seconds |
| Started | Aug 23 05:13:15 PM UTC 24 |
| Finished | Aug 23 05:13:26 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188530090 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.1188530090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.123509581 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2673119248 ps |
| CPU time | 3.72 seconds |
| Started | Aug 23 05:13:14 PM UTC 24 |
| Finished | Aug 23 05:13:19 PM UTC 24 |
| Peak memory | 215388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123509581 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.123509581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.318417791 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 289207445 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 05:13:14 PM UTC 24 |
| Finished | Aug 23 05:13:16 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318417791 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.318417791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2228526331 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 208116201 ps |
| CPU time | 3.09 seconds |
| Started | Aug 23 05:13:17 PM UTC 24 |
| Finished | Aug 23 05:13:21 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228526331 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.2228526331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.2451148420 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 245740327 ps |
| CPU time | 2.88 seconds |
| Started | Aug 23 05:13:15 PM UTC 24 |
| Finished | Aug 23 05:13:19 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451148420 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2451148420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.349535326 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1187265640 ps |
| CPU time | 9.84 seconds |
| Started | Aug 23 05:13:16 PM UTC 24 |
| Finished | Aug 23 05:13:27 PM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349535326 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.349535326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1941508481 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 114059368 ps |
| CPU time | 2 seconds |
| Started | Aug 23 05:13:21 PM UTC 24 |
| Finished | Aug 23 05:13:25 PM UTC 24 |
| Peak memory | 229176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1941508481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ rand_reset.1941508481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.1876220855 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 149781757 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 05:13:21 PM UTC 24 |
| Finished | Aug 23 05:13:24 PM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876220855 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1876220855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.746376412 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 52016019 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:13:19 PM UTC 24 |
| Finished | Aug 23 05:13:21 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746376412 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.746376412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3357676700 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5947501846 ps |
| CPU time | 11.69 seconds |
| Started | Aug 23 05:13:19 PM UTC 24 |
| Finished | Aug 23 05:13:32 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357676700 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.3357676700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3891941314 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 398243626 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 05:13:19 PM UTC 24 |
| Finished | Aug 23 05:13:21 PM UTC 24 |
| Peak memory | 214000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891941314 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.3891941314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.200269105 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1097116053 ps |
| CPU time | 3.98 seconds |
| Started | Aug 23 05:13:21 PM UTC 24 |
| Finished | Aug 23 05:13:26 PM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200269105 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.200269105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.2145424238 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 164267506 ps |
| CPU time | 2.63 seconds |
| Started | Aug 23 05:13:20 PM UTC 24 |
| Finished | Aug 23 05:13:24 PM UTC 24 |
| Peak memory | 227764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145424238 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2145424238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3384171701 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3179698331 ps |
| CPU time | 9.01 seconds |
| Started | Aug 23 05:13:20 PM UTC 24 |
| Finished | Aug 23 05:13:31 PM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384171701 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3384171701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1925339000 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 302523711 ps |
| CPU time | 1.71 seconds |
| Started | Aug 23 05:13:25 PM UTC 24 |
| Finished | Aug 23 05:13:27 PM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1925339000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.1925339000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.2439756047 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 109801755 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 05:13:25 PM UTC 24 |
| Finished | Aug 23 05:13:27 PM UTC 24 |
| Peak memory | 224864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439756047 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2439756047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3471183056 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 65800866017 ps |
| CPU time | 52.66 seconds |
| Started | Aug 23 05:13:22 PM UTC 24 |
| Finished | Aug 23 05:14:17 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471183056 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.3471183056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1217273382 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1937887772 ps |
| CPU time | 1.36 seconds |
| Started | Aug 23 05:13:22 PM UTC 24 |
| Finished | Aug 23 05:13:25 PM UTC 24 |
| Peak memory | 215124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217273382 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.1217273382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2443641725 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 853608646 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 05:13:22 PM UTC 24 |
| Finished | Aug 23 05:13:27 PM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443641725 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.2443641725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.818222120 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 212450119 ps |
| CPU time | 3.47 seconds |
| Started | Aug 23 05:13:25 PM UTC 24 |
| Finished | Aug 23 05:13:29 PM UTC 24 |
| Peak memory | 214632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818222120 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.818222120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.2854956273 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 520582013 ps |
| CPU time | 3.03 seconds |
| Started | Aug 23 05:13:24 PM UTC 24 |
| Finished | Aug 23 05:13:28 PM UTC 24 |
| Peak memory | 225308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854956273 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2854956273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.745648026 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 84534211 ps |
| CPU time | 3.31 seconds |
| Started | Aug 23 05:13:27 PM UTC 24 |
| Finished | Aug 23 05:13:32 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=745648026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_r and_reset.745648026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.3834050039 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 351091323 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 05:13:27 PM UTC 24 |
| Finished | Aug 23 05:13:30 PM UTC 24 |
| Peak memory | 229224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834050039 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3834050039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1724641886 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 17762118739 ps |
| CPU time | 10.94 seconds |
| Started | Aug 23 05:13:26 PM UTC 24 |
| Finished | Aug 23 05:13:38 PM UTC 24 |
| Peak memory | 215424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724641886 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.1724641886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1686837931 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4055445183 ps |
| CPU time | 6.36 seconds |
| Started | Aug 23 05:13:26 PM UTC 24 |
| Finished | Aug 23 05:13:34 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686837931 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.1686837931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2088197349 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 284563848 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 05:13:26 PM UTC 24 |
| Finished | Aug 23 05:13:28 PM UTC 24 |
| Peak memory | 214768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088197349 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.2088197349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1870109012 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 622991743 ps |
| CPU time | 3.99 seconds |
| Started | Aug 23 05:13:27 PM UTC 24 |
| Finished | Aug 23 05:13:33 PM UTC 24 |
| Peak memory | 215372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870109012 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.1870109012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.2077823614 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 269711613 ps |
| CPU time | 3.44 seconds |
| Started | Aug 23 05:13:26 PM UTC 24 |
| Finished | Aug 23 05:13:31 PM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077823614 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2077823614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3791025230 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 89448827 ps |
| CPU time | 2.75 seconds |
| Started | Aug 23 05:13:30 PM UTC 24 |
| Finished | Aug 23 05:13:35 PM UTC 24 |
| Peak memory | 231904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3791025230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_ rand_reset.3791025230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.1701785231 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 74176684 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 05:13:29 PM UTC 24 |
| Finished | Aug 23 05:13:32 PM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701785231 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1701785231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3910274838 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 15799493709 ps |
| CPU time | 25.5 seconds |
| Started | Aug 23 05:13:28 PM UTC 24 |
| Finished | Aug 23 05:13:55 PM UTC 24 |
| Peak memory | 215492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910274838 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.3910274838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2409679417 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3318487031 ps |
| CPU time | 4.75 seconds |
| Started | Aug 23 05:13:28 PM UTC 24 |
| Finished | Aug 23 05:13:35 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409679417 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.2409679417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3057218426 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 149668586 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 05:13:28 PM UTC 24 |
| Finished | Aug 23 05:13:31 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057218426 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.3057218426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3189712577 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 350693110 ps |
| CPU time | 3.95 seconds |
| Started | Aug 23 05:13:29 PM UTC 24 |
| Finished | Aug 23 05:13:35 PM UTC 24 |
| Peak memory | 215364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189712577 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.3189712577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.665003876 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 150499667 ps |
| CPU time | 3.64 seconds |
| Started | Aug 23 05:13:28 PM UTC 24 |
| Finished | Aug 23 05:13:34 PM UTC 24 |
| Peak memory | 225796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665003876 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.665003876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.677337121 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1766678973 ps |
| CPU time | 13.7 seconds |
| Started | Aug 23 05:13:28 PM UTC 24 |
| Finished | Aug 23 05:13:44 PM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677337121 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.677337121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1374287764 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 132768887 ps |
| CPU time | 1.51 seconds |
| Started | Aug 23 05:13:34 PM UTC 24 |
| Finished | Aug 23 05:13:37 PM UTC 24 |
| Peak memory | 227252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1374287764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_ rand_reset.1374287764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.1486674508 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 239270664 ps |
| CPU time | 1.45 seconds |
| Started | Aug 23 05:13:33 PM UTC 24 |
| Finished | Aug 23 05:13:35 PM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486674508 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1486674508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1754246447 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2269086370 ps |
| CPU time | 5.13 seconds |
| Started | Aug 23 05:13:31 PM UTC 24 |
| Finished | Aug 23 05:13:38 PM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754246447 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.1754246447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.568663905 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2558779163 ps |
| CPU time | 3.1 seconds |
| Started | Aug 23 05:13:31 PM UTC 24 |
| Finished | Aug 23 05:13:36 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568663905 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.568663905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3498744714 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 414859831 ps |
| CPU time | 1.58 seconds |
| Started | Aug 23 05:13:31 PM UTC 24 |
| Finished | Aug 23 05:13:34 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498744714 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.3498744714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1527137005 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 378816390 ps |
| CPU time | 5.75 seconds |
| Started | Aug 23 05:13:33 PM UTC 24 |
| Finished | Aug 23 05:13:40 PM UTC 24 |
| Peak memory | 215508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527137005 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.1527137005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3236262542 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1552340265 ps |
| CPU time | 4.17 seconds |
| Started | Aug 23 05:13:31 PM UTC 24 |
| Finished | Aug 23 05:13:37 PM UTC 24 |
| Peak memory | 225956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236262542 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3236262542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1639286580 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1303851972 ps |
| CPU time | 10.04 seconds |
| Started | Aug 23 05:13:32 PM UTC 24 |
| Finished | Aug 23 05:13:44 PM UTC 24 |
| Peak memory | 225668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639286580 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1639286580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2593676364 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2837426354 ps |
| CPU time | 22.08 seconds |
| Started | Aug 23 05:11:47 PM UTC 24 |
| Finished | Aug 23 05:12:11 PM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593676364 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.2593676364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1526504962 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 91256926727 ps |
| CPU time | 67.93 seconds |
| Started | Aug 23 05:11:56 PM UTC 24 |
| Finished | Aug 23 05:13:05 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526504962 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1526504962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1723047599 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 180472763 ps |
| CPU time | 1.71 seconds |
| Started | Aug 23 05:11:55 PM UTC 24 |
| Finished | Aug 23 05:11:58 PM UTC 24 |
| Peak memory | 224516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723047599 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1723047599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2223252482 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 222540706 ps |
| CPU time | 3.25 seconds |
| Started | Aug 23 05:11:57 PM UTC 24 |
| Finished | Aug 23 05:12:01 PM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2223252482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_r and_reset.2223252482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2974855485 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 130469420 ps |
| CPU time | 1.78 seconds |
| Started | Aug 23 05:11:55 PM UTC 24 |
| Finished | Aug 23 05:11:58 PM UTC 24 |
| Peak memory | 225204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974855485 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2974855485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4201811853 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 71522297306 ps |
| CPU time | 90.68 seconds |
| Started | Aug 23 05:11:50 PM UTC 24 |
| Finished | Aug 23 05:13:23 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201811853 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.4201811853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1841840547 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 55933676630 ps |
| CPU time | 92.32 seconds |
| Started | Aug 23 05:11:50 PM UTC 24 |
| Finished | Aug 23 05:13:25 PM UTC 24 |
| Peak memory | 215096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841840547 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.1841840547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2182557437 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 4450312878 ps |
| CPU time | 3.74 seconds |
| Started | Aug 23 05:11:49 PM UTC 24 |
| Finished | Aug 23 05:11:54 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182557437 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.2182557437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.575551960 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 4728398412 ps |
| CPU time | 3.68 seconds |
| Started | Aug 23 05:11:49 PM UTC 24 |
| Finished | Aug 23 05:11:54 PM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575551960 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.575551960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1515859092 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 228101672 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 05:11:48 PM UTC 24 |
| Finished | Aug 23 05:11:50 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515859092 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.1515859092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3676713886 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 16772474689 ps |
| CPU time | 14.29 seconds |
| Started | Aug 23 05:11:48 PM UTC 24 |
| Finished | Aug 23 05:12:04 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676713886 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.3676713886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3233487724 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 272670978 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 05:11:48 PM UTC 24 |
| Finished | Aug 23 05:11:50 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233487724 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.3233487724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2524356396 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 611722229 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 05:11:48 PM UTC 24 |
| Finished | Aug 23 05:11:50 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524356396 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2524356396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.117178342 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 148714162 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:11:55 PM UTC 24 |
| Finished | Aug 23 05:11:56 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117178342 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.117178342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3095474119 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 36213866 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:11:54 PM UTC 24 |
| Finished | Aug 23 05:11:55 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095474119 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3095474119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.90189121 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 637678000 ps |
| CPU time | 7.13 seconds |
| Started | Aug 23 05:11:57 PM UTC 24 |
| Finished | Aug 23 05:12:05 PM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90189121 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.90189121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1171545817 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4511189618 ps |
| CPU time | 40.76 seconds |
| Started | Aug 23 05:11:51 PM UTC 24 |
| Finished | Aug 23 05:12:34 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1171545817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_re set.1171545817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.4130087029 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 169776843 ps |
| CPU time | 3.18 seconds |
| Started | Aug 23 05:11:51 PM UTC 24 |
| Finished | Aug 23 05:11:56 PM UTC 24 |
| Peak memory | 225804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130087029 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4130087029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.290147896 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1025807293 ps |
| CPU time | 9.67 seconds |
| Started | Aug 23 05:11:54 PM UTC 24 |
| Finished | Aug 23 05:12:04 PM UTC 24 |
| Peak memory | 225656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290147896 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.290147896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1792824754 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 38252539566 ps |
| CPU time | 65.52 seconds |
| Started | Aug 23 05:12:07 PM UTC 24 |
| Finished | Aug 23 05:13:14 PM UTC 24 |
| Peak memory | 225764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792824754 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1792824754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1018201260 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 122630200 ps |
| CPU time | 1.44 seconds |
| Started | Aug 23 05:12:06 PM UTC 24 |
| Finished | Aug 23 05:12:08 PM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018201260 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1018201260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2585214180 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 259475694 ps |
| CPU time | 1.77 seconds |
| Started | Aug 23 05:12:09 PM UTC 24 |
| Finished | Aug 23 05:12:12 PM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2585214180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r and_reset.2585214180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.444075266 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 164793170 ps |
| CPU time | 2.13 seconds |
| Started | Aug 23 05:12:06 PM UTC 24 |
| Finished | Aug 23 05:12:09 PM UTC 24 |
| Peak memory | 225696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444075266 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.444075266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1049278984 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 32773044742 ps |
| CPU time | 28.51 seconds |
| Started | Aug 23 05:12:02 PM UTC 24 |
| Finished | Aug 23 05:12:32 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049278984 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.1049278984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3430281416 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 43793138585 ps |
| CPU time | 38.05 seconds |
| Started | Aug 23 05:12:02 PM UTC 24 |
| Finished | Aug 23 05:12:42 PM UTC 24 |
| Peak memory | 215068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430281416 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.3430281416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3282418919 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1620503916 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 05:11:59 PM UTC 24 |
| Finished | Aug 23 05:12:02 PM UTC 24 |
| Peak memory | 215224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282418919 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.3282418919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4117593944 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2812342103 ps |
| CPU time | 9.11 seconds |
| Started | Aug 23 05:12:00 PM UTC 24 |
| Finished | Aug 23 05:12:11 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117593944 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.4117593944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2727649789 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 582111511 ps |
| CPU time | 1.91 seconds |
| Started | Aug 23 05:11:58 PM UTC 24 |
| Finished | Aug 23 05:12:01 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727649789 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.2727649789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1341434300 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2296692632 ps |
| CPU time | 2.63 seconds |
| Started | Aug 23 05:11:58 PM UTC 24 |
| Finished | Aug 23 05:12:02 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341434300 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.1341434300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2333874490 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 624544549 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 05:11:57 PM UTC 24 |
| Finished | Aug 23 05:11:59 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333874490 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.2333874490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1864559953 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 274401410 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 05:11:57 PM UTC 24 |
| Finished | Aug 23 05:11:59 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864559953 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1864559953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.225175279 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 79416216 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:12:06 PM UTC 24 |
| Finished | Aug 23 05:12:08 PM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225175279 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.225175279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.2826487535 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 138065214 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 05:12:06 PM UTC 24 |
| Finished | Aug 23 05:12:08 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826487535 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2826487535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.639709539 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1675486702 ps |
| CPU time | 4.08 seconds |
| Started | Aug 23 05:12:09 PM UTC 24 |
| Finished | Aug 23 05:12:14 PM UTC 24 |
| Peak memory | 215560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639709539 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.639709539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4291834335 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3473180810 ps |
| CPU time | 68.99 seconds |
| Started | Aug 23 05:12:02 PM UTC 24 |
| Finished | Aug 23 05:13:13 PM UTC 24 |
| Peak memory | 229832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4291834335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_re set.4291834335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.3447069414 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 308379926 ps |
| CPU time | 3.58 seconds |
| Started | Aug 23 05:12:03 PM UTC 24 |
| Finished | Aug 23 05:12:08 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447069414 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3447069414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2204977700 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 4102521153 ps |
| CPU time | 16.86 seconds |
| Started | Aug 23 05:12:04 PM UTC 24 |
| Finished | Aug 23 05:12:23 PM UTC 24 |
| Peak memory | 232580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204977700 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2204977700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2430679028 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 634305271 ps |
| CPU time | 23.76 seconds |
| Started | Aug 23 05:12:09 PM UTC 24 |
| Finished | Aug 23 05:12:34 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430679028 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.2430679028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3803800841 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 19513956237 ps |
| CPU time | 59.31 seconds |
| Started | Aug 23 05:12:23 PM UTC 24 |
| Finished | Aug 23 05:13:24 PM UTC 24 |
| Peak memory | 225700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803800841 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3803800841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1326822270 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 152039733 ps |
| CPU time | 1.51 seconds |
| Started | Aug 23 05:12:23 PM UTC 24 |
| Finished | Aug 23 05:12:26 PM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326822270 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1326822270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2445185558 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 174113553 ps |
| CPU time | 3.74 seconds |
| Started | Aug 23 05:12:24 PM UTC 24 |
| Finished | Aug 23 05:12:29 PM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2445185558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r and_reset.2445185558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.1673178989 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 92772059 ps |
| CPU time | 1.46 seconds |
| Started | Aug 23 05:12:23 PM UTC 24 |
| Finished | Aug 23 05:12:26 PM UTC 24 |
| Peak memory | 225204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673178989 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1673178989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.643292369 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 87557842567 ps |
| CPU time | 213.67 seconds |
| Started | Aug 23 05:12:12 PM UTC 24 |
| Finished | Aug 23 05:15:49 PM UTC 24 |
| Peak memory | 215384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643292369 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.643292369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.206207791 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 48493476172 ps |
| CPU time | 103.05 seconds |
| Started | Aug 23 05:12:12 PM UTC 24 |
| Finished | Aug 23 05:13:57 PM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206207791 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.206207791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.382101115 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 7223999495 ps |
| CPU time | 21.2 seconds |
| Started | Aug 23 05:12:11 PM UTC 24 |
| Finished | Aug 23 05:12:33 PM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382101115 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.382101115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1875819758 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3102232396 ps |
| CPU time | 3.81 seconds |
| Started | Aug 23 05:12:11 PM UTC 24 |
| Finished | Aug 23 05:12:16 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875819758 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1875819758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4090522267 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 204617927 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 05:12:10 PM UTC 24 |
| Finished | Aug 23 05:12:12 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090522267 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.4090522267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2224088025 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 25826722593 ps |
| CPU time | 33.74 seconds |
| Started | Aug 23 05:12:10 PM UTC 24 |
| Finished | Aug 23 05:12:45 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224088025 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.2224088025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4172855778 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 208002781 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 05:12:09 PM UTC 24 |
| Finished | Aug 23 05:12:11 PM UTC 24 |
| Peak memory | 213332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172855778 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.4172855778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3750170725 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 461184590 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 05:12:09 PM UTC 24 |
| Finished | Aug 23 05:12:11 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750170725 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3750170725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2626197830 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 43748445 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:12:22 PM UTC 24 |
| Finished | Aug 23 05:12:24 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626197830 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.2626197830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.3996650265 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 144112144 ps |
| CPU time | 0.94 seconds |
| Started | Aug 23 05:12:22 PM UTC 24 |
| Finished | Aug 23 05:12:24 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996650265 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3996650265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3005154880 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1001180854 ps |
| CPU time | 3.96 seconds |
| Started | Aug 23 05:12:23 PM UTC 24 |
| Finished | Aug 23 05:12:28 PM UTC 24 |
| Peak memory | 215356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005154880 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.3005154880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.302145889 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 3300418484 ps |
| CPU time | 31.15 seconds |
| Started | Aug 23 05:12:12 PM UTC 24 |
| Finished | Aug 23 05:12:45 PM UTC 24 |
| Peak memory | 225924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=302145889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.302145889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1961112296 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 182361732 ps |
| CPU time | 4.02 seconds |
| Started | Aug 23 05:12:13 PM UTC 24 |
| Finished | Aug 23 05:12:18 PM UTC 24 |
| Peak memory | 227836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961112296 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1961112296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3397203816 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 130676632 ps |
| CPU time | 2.52 seconds |
| Started | Aug 23 05:12:35 PM UTC 24 |
| Finished | Aug 23 05:12:39 PM UTC 24 |
| Peak memory | 229824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3397203816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_r and_reset.3397203816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.1251728164 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 424028744 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 05:12:33 PM UTC 24 |
| Finished | Aug 23 05:12:36 PM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251728164 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1251728164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1931830362 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2251586730 ps |
| CPU time | 6.02 seconds |
| Started | Aug 23 05:12:27 PM UTC 24 |
| Finished | Aug 23 05:12:34 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931830362 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.1931830362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1993689650 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 15156895947 ps |
| CPU time | 23.24 seconds |
| Started | Aug 23 05:12:26 PM UTC 24 |
| Finished | Aug 23 05:12:51 PM UTC 24 |
| Peak memory | 215380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993689650 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1993689650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3817053682 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 610097663 ps |
| CPU time | 0.95 seconds |
| Started | Aug 23 05:12:24 PM UTC 24 |
| Finished | Aug 23 05:12:26 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817053682 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3817053682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2782020295 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 192740236 ps |
| CPU time | 3.18 seconds |
| Started | Aug 23 05:12:34 PM UTC 24 |
| Finished | Aug 23 05:12:38 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782020295 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.2782020295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1028994032 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1690828812 ps |
| CPU time | 35.12 seconds |
| Started | Aug 23 05:12:28 PM UTC 24 |
| Finished | Aug 23 05:13:04 PM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1028994032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re set.1028994032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.4215527828 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 365896239 ps |
| CPU time | 5.09 seconds |
| Started | Aug 23 05:12:30 PM UTC 24 |
| Finished | Aug 23 05:12:36 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215527828 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4215527828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3586473211 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5213671497 ps |
| CPU time | 17.41 seconds |
| Started | Aug 23 05:12:30 PM UTC 24 |
| Finished | Aug 23 05:12:48 PM UTC 24 |
| Peak memory | 232444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586473211 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3586473211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.244052176 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 225312098 ps |
| CPU time | 3.34 seconds |
| Started | Aug 23 05:12:39 PM UTC 24 |
| Finished | Aug 23 05:12:44 PM UTC 24 |
| Peak memory | 231824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=244052176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_ra nd_reset.244052176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.1042919042 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 221595826 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 05:12:38 PM UTC 24 |
| Finished | Aug 23 05:12:41 PM UTC 24 |
| Peak memory | 225644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042919042 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1042919042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3211281150 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 19143964983 ps |
| CPU time | 45.65 seconds |
| Started | Aug 23 05:12:35 PM UTC 24 |
| Finished | Aug 23 05:13:22 PM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211281150 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.3211281150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1864735059 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 7329052407 ps |
| CPU time | 7.3 seconds |
| Started | Aug 23 05:12:35 PM UTC 24 |
| Finished | Aug 23 05:12:44 PM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864735059 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1864735059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2777956940 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 941592373 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 05:12:35 PM UTC 24 |
| Finished | Aug 23 05:12:37 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777956940 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2777956940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3725457357 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1710988771 ps |
| CPU time | 6.83 seconds |
| Started | Aug 23 05:12:39 PM UTC 24 |
| Finished | Aug 23 05:12:47 PM UTC 24 |
| Peak memory | 215428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725457357 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.3725457357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.708076805 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4568781498 ps |
| CPU time | 48.82 seconds |
| Started | Aug 23 05:12:35 PM UTC 24 |
| Finished | Aug 23 05:13:26 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=708076805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.708076805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2554599798 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 108042805 ps |
| CPU time | 2.13 seconds |
| Started | Aug 23 05:12:37 PM UTC 24 |
| Finished | Aug 23 05:12:40 PM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554599798 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2554599798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1578197324 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2048542578 ps |
| CPU time | 8.72 seconds |
| Started | Aug 23 05:12:37 PM UTC 24 |
| Finished | Aug 23 05:12:47 PM UTC 24 |
| Peak memory | 232348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578197324 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1578197324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2707544409 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 312606276 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 05:12:45 PM UTC 24 |
| Finished | Aug 23 05:12:49 PM UTC 24 |
| Peak memory | 231904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2707544409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r and_reset.2707544409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1095089072 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 25470815650 ps |
| CPU time | 70.69 seconds |
| Started | Aug 23 05:12:42 PM UTC 24 |
| Finished | Aug 23 05:13:54 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095089072 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.1095089072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.686620649 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4829466079 ps |
| CPU time | 11.79 seconds |
| Started | Aug 23 05:12:41 PM UTC 24 |
| Finished | Aug 23 05:12:54 PM UTC 24 |
| Peak memory | 215320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686620649 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.686620649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.249058746 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1045817786 ps |
| CPU time | 3.08 seconds |
| Started | Aug 23 05:12:39 PM UTC 24 |
| Finished | Aug 23 05:12:44 PM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249058746 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.249058746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2256637674 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 734358503 ps |
| CPU time | 7.13 seconds |
| Started | Aug 23 05:12:45 PM UTC 24 |
| Finished | Aug 23 05:12:53 PM UTC 24 |
| Peak memory | 215556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256637674 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.2256637674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.1336491931 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 168876264 ps |
| CPU time | 3.9 seconds |
| Started | Aug 23 05:12:43 PM UTC 24 |
| Finished | Aug 23 05:12:48 PM UTC 24 |
| Peak memory | 225788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336491931 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1336491931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3616188143 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2846985701 ps |
| CPU time | 13.59 seconds |
| Started | Aug 23 05:12:45 PM UTC 24 |
| Finished | Aug 23 05:12:59 PM UTC 24 |
| Peak memory | 225860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616188143 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3616188143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3011894572 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 96016256 ps |
| CPU time | 2.54 seconds |
| Started | Aug 23 05:12:49 PM UTC 24 |
| Finished | Aug 23 05:12:53 PM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=3011894572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.3011894572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2588505823 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 135467301 ps |
| CPU time | 1.52 seconds |
| Started | Aug 23 05:12:49 PM UTC 24 |
| Finished | Aug 23 05:12:52 PM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588505823 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2588505823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1535829146 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 12099408739 ps |
| CPU time | 7.17 seconds |
| Started | Aug 23 05:12:48 PM UTC 24 |
| Finished | Aug 23 05:12:56 PM UTC 24 |
| Peak memory | 215336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535829146 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.1535829146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3293948004 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 5264588173 ps |
| CPU time | 4.15 seconds |
| Started | Aug 23 05:12:46 PM UTC 24 |
| Finished | Aug 23 05:12:51 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293948004 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3293948004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1455363174 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 668558304 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 05:12:46 PM UTC 24 |
| Finished | Aug 23 05:12:48 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455363174 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1455363174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2838964445 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3685362801 ps |
| CPU time | 7.93 seconds |
| Started | Aug 23 05:12:49 PM UTC 24 |
| Finished | Aug 23 05:12:58 PM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838964445 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.2838964445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3015599285 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3073706004 ps |
| CPU time | 42.41 seconds |
| Started | Aug 23 05:12:48 PM UTC 24 |
| Finished | Aug 23 05:13:32 PM UTC 24 |
| Peak memory | 232460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3015599285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_re set.3015599285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1140333946 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 175848347 ps |
| CPU time | 3.87 seconds |
| Started | Aug 23 05:12:48 PM UTC 24 |
| Finished | Aug 23 05:12:53 PM UTC 24 |
| Peak memory | 225852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140333946 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1140333946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2636380079 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3448033677 ps |
| CPU time | 9.19 seconds |
| Started | Aug 23 05:12:48 PM UTC 24 |
| Finished | Aug 23 05:12:58 PM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636380079 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2636380079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.125773275 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 84771726 ps |
| CPU time | 2.28 seconds |
| Started | Aug 23 05:12:56 PM UTC 24 |
| Finished | Aug 23 05:13:00 PM UTC 24 |
| Peak memory | 229928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=125773275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_ra nd_reset.125773275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3505074061 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1604936434 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 05:12:54 PM UTC 24 |
| Finished | Aug 23 05:12:58 PM UTC 24 |
| Peak memory | 229684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505074061 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3505074061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2492407853 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3402051637 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 05:12:52 PM UTC 24 |
| Finished | Aug 23 05:12:56 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492407853 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.2492407853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2456943832 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1583641416 ps |
| CPU time | 2.14 seconds |
| Started | Aug 23 05:12:52 PM UTC 24 |
| Finished | Aug 23 05:12:55 PM UTC 24 |
| Peak memory | 215296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456943832 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2456943832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.355239675 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 168058742 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 05:12:52 PM UTC 24 |
| Finished | Aug 23 05:12:54 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355239675 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.355239675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3485909565 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1165435685 ps |
| CPU time | 6.14 seconds |
| Started | Aug 23 05:12:55 PM UTC 24 |
| Finished | Aug 23 05:13:03 PM UTC 24 |
| Peak memory | 215584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485909565 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.3485909565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3363152569 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 4962768401 ps |
| CPU time | 50.59 seconds |
| Started | Aug 23 05:12:53 PM UTC 24 |
| Finished | Aug 23 05:13:45 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3363152569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.3363152569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.3296373131 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 301531768 ps |
| CPU time | 4.47 seconds |
| Started | Aug 23 05:12:53 PM UTC 24 |
| Finished | Aug 23 05:12:59 PM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296373131 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3296373131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2913264740 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2134362282 ps |
| CPU time | 8.34 seconds |
| Started | Aug 23 05:12:54 PM UTC 24 |
| Finished | Aug 23 05:13:04 PM UTC 24 |
| Peak memory | 227840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913264740 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2913264740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.4156731162 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 32998234177 ps |
| CPU time | 85.63 seconds |
| Started | Aug 23 05:13:36 PM UTC 24 |
| Finished | Aug 23 05:15:03 PM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156731162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4156731162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.139256027 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1198556729 ps |
| CPU time | 1.63 seconds |
| Started | Aug 23 05:13:35 PM UTC 24 |
| Finished | Aug 23 05:13:38 PM UTC 24 |
| Peak memory | 215484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139256027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.139256027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1341865059 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 273704313 ps |
| CPU time | 1.44 seconds |
| Started | Aug 23 05:13:42 PM UTC 24 |
| Finished | Aug 23 05:13:44 PM UTC 24 |
| Peak memory | 256816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341865059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.1341865059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4093595082 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 876648096 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 05:13:36 PM UTC 24 |
| Finished | Aug 23 05:13:38 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093595082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4093595082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.924862839 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 783856884 ps |
| CPU time | 2.45 seconds |
| Started | Aug 23 05:13:36 PM UTC 24 |
| Finished | Aug 23 05:13:40 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924862839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.924862839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.2213538979 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 399497122 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 05:13:38 PM UTC 24 |
| Finished | Aug 23 05:13:40 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213538979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2213538979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.4247476880 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 201768018 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 05:13:41 PM UTC 24 |
| Finished | Aug 23 05:13:42 PM UTC 24 |
| Peak memory | 236008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247476880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.4247476880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3960237930 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2483436572 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 05:13:35 PM UTC 24 |
| Finished | Aug 23 05:13:38 PM UTC 24 |
| Peak memory | 216252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960237930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.3960237930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.859466009 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 113921182 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 05:13:38 PM UTC 24 |
| Finished | Aug 23 05:13:40 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859466009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.859466009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.3954840453 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 51322005 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 05:13:41 PM UTC 24 |
| Finished | Aug 23 05:13:43 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954840453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3954840453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1447849660 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 546666351 ps |
| CPU time | 1.86 seconds |
| Started | Aug 23 05:13:39 PM UTC 24 |
| Finished | Aug 23 05:13:42 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447849660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1447849660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2208149632 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1791042201 ps |
| CPU time | 2.11 seconds |
| Started | Aug 23 05:13:39 PM UTC 24 |
| Finished | Aug 23 05:13:43 PM UTC 24 |
| Peak memory | 215816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208149632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2208149632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3015137184 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 270838189 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 05:13:39 PM UTC 24 |
| Finished | Aug 23 05:13:42 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015137184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3015137184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.496359399 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 111709948 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 05:13:37 PM UTC 24 |
| Finished | Aug 23 05:13:39 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496359399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.496359399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.1756304492 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 330454339 ps |
| CPU time | 1.34 seconds |
| Started | Aug 23 05:13:37 PM UTC 24 |
| Finished | Aug 23 05:13:39 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756304492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1756304492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.1675963997 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 317825648 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 05:13:39 PM UTC 24 |
| Finished | Aug 23 05:13:42 PM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675963997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1675963997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.3079981322 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 261958591 ps |
| CPU time | 0.93 seconds |
| Started | Aug 23 05:13:40 PM UTC 24 |
| Finished | Aug 23 05:13:43 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079981322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3079981322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.370871958 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2646627046 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 05:13:39 PM UTC 24 |
| Finished | Aug 23 05:13:44 PM UTC 24 |
| Peak memory | 216076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370871958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.370871958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1678479861 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1175974885 ps |
| CPU time | 2.33 seconds |
| Started | Aug 23 05:13:43 PM UTC 24 |
| Finished | Aug 23 05:13:46 PM UTC 24 |
| Peak memory | 254424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678479861 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1678479861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3391940339 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2089501863 ps |
| CPU time | 2.78 seconds |
| Started | Aug 23 05:13:34 PM UTC 24 |
| Finished | Aug 23 05:13:38 PM UTC 24 |
| Peak memory | 216068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391940339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3391940339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.1662096915 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8232405266 ps |
| CPU time | 45.85 seconds |
| Started | Aug 23 05:13:43 PM UTC 24 |
| Finished | Aug 23 05:14:30 PM UTC 24 |
| Peak memory | 233316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1662096915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres s_all_with_rand_reset.1662096915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3374482253 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 130378023 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 05:13:48 PM UTC 24 |
| Finished | Aug 23 05:13:50 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374482253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3374482253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.2013673497 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 94232224 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 05:13:51 PM UTC 24 |
| Finished | Aug 23 05:13:53 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013673497 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2013673497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2832473283 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2020506902 ps |
| CPU time | 5.87 seconds |
| Started | Aug 23 05:13:44 PM UTC 24 |
| Finished | Aug 23 05:13:51 PM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832473283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2832473283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.2533933824 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4205946096 ps |
| CPU time | 6.88 seconds |
| Started | Aug 23 05:13:44 PM UTC 24 |
| Finished | Aug 23 05:13:52 PM UTC 24 |
| Peak memory | 226624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533933824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2533933824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.2521766769 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1161280337 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 05:13:44 PM UTC 24 |
| Finished | Aug 23 05:13:47 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521766769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2521766769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.600899970 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 873952107 ps |
| CPU time | 1.13 seconds |
| Started | Aug 23 05:13:45 PM UTC 24 |
| Finished | Aug 23 05:13:48 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600899970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.600899970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.366958012 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1043412964 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 05:13:45 PM UTC 24 |
| Finished | Aug 23 05:13:50 PM UTC 24 |
| Peak memory | 216000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366958012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.366958012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.199904267 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 313143988 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 05:13:45 PM UTC 24 |
| Finished | Aug 23 05:13:47 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199904267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.199904267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1161341352 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 159268865 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:13:45 PM UTC 24 |
| Finished | Aug 23 05:13:47 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161341352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1161341352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.1585452627 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 168648958 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 05:13:49 PM UTC 24 |
| Finished | Aug 23 05:13:51 PM UTC 24 |
| Peak memory | 235492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585452627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1585452627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2074484361 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2187526553 ps |
| CPU time | 2.98 seconds |
| Started | Aug 23 05:13:44 PM UTC 24 |
| Finished | Aug 23 05:13:48 PM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074484361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.2074484361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2190013737 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 161254611 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 05:13:49 PM UTC 24 |
| Finished | Aug 23 05:13:51 PM UTC 24 |
| Peak memory | 215332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190013737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2190013737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.3289000097 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 183777213 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 05:13:45 PM UTC 24 |
| Finished | Aug 23 05:13:48 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289000097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3289000097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.911360000 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 69869107 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:13:45 PM UTC 24 |
| Finished | Aug 23 05:13:47 PM UTC 24 |
| Peak memory | 213324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911360000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.911360000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3176731340 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 443380181 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 05:13:48 PM UTC 24 |
| Finished | Aug 23 05:13:50 PM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176731340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3176731340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2811368846 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 436542766 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 05:13:48 PM UTC 24 |
| Finished | Aug 23 05:13:50 PM UTC 24 |
| Peak memory | 213380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811368846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2811368846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1865729186 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 588321808 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 05:13:48 PM UTC 24 |
| Finished | Aug 23 05:13:50 PM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865729186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1865729186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3802137677 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 134392739 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:13:48 PM UTC 24 |
| Finished | Aug 23 05:13:50 PM UTC 24 |
| Peak memory | 213444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802137677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3802137677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2370891256 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 621839388 ps |
| CPU time | 2.39 seconds |
| Started | Aug 23 05:13:45 PM UTC 24 |
| Finished | Aug 23 05:13:49 PM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370891256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2370891256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.3275579071 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 316769063 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:13:45 PM UTC 24 |
| Finished | Aug 23 05:13:47 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275579071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3275579071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.3858822920 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 400003726 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 05:13:48 PM UTC 24 |
| Finished | Aug 23 05:13:50 PM UTC 24 |
| Peak memory | 225880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858822920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3858822920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2595747350 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 166367202 ps |
| CPU time | 1.09 seconds |
| Started | Aug 23 05:13:49 PM UTC 24 |
| Finished | Aug 23 05:13:51 PM UTC 24 |
| Peak memory | 215668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595747350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2595747350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2404054821 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 57209709 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 05:13:49 PM UTC 24 |
| Finished | Aug 23 05:13:51 PM UTC 24 |
| Peak memory | 225460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404054821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2404054821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.3883335853 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 8828688597 ps |
| CPU time | 13.9 seconds |
| Started | Aug 23 05:13:44 PM UTC 24 |
| Finished | Aug 23 05:13:59 PM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883335853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3883335853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.2609691421 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1293768197 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 05:13:44 PM UTC 24 |
| Finished | Aug 23 05:13:47 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609691421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2609691421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3467544614 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 4977149037 ps |
| CPU time | 43.82 seconds |
| Started | Aug 23 05:13:51 PM UTC 24 |
| Finished | Aug 23 05:14:37 PM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3467544614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.3467544614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3304163517 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 77941361 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:14:28 PM UTC 24 |
| Finished | Aug 23 05:14:30 PM UTC 24 |
| Peak memory | 215820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304163517 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3304163517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.2316279008 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9073852219 ps |
| CPU time | 19.85 seconds |
| Started | Aug 23 05:14:26 PM UTC 24 |
| Finished | Aug 23 05:14:47 PM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316279008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2316279008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1595793092 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2166629294 ps |
| CPU time | 3.82 seconds |
| Started | Aug 23 05:14:26 PM UTC 24 |
| Finished | Aug 23 05:14:30 PM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595793092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1595793092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.694967383 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3273193186 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 05:14:26 PM UTC 24 |
| Finished | Aug 23 05:14:30 PM UTC 24 |
| Peak memory | 226432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694967383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.694967383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3048644321 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 7340422785 ps |
| CPU time | 11.68 seconds |
| Started | Aug 23 05:14:24 PM UTC 24 |
| Finished | Aug 23 05:14:37 PM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048644321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3048644321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.1647517374 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2382969394 ps |
| CPU time | 3.68 seconds |
| Started | Aug 23 05:14:26 PM UTC 24 |
| Finished | Aug 23 05:14:30 PM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647517374 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1647517374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.487740607 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 35160907 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 05:14:30 PM UTC 24 |
| Finished | Aug 23 05:14:32 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487740607 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.487740607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3623006093 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1360725617 ps |
| CPU time | 4.62 seconds |
| Started | Aug 23 05:14:28 PM UTC 24 |
| Finished | Aug 23 05:14:34 PM UTC 24 |
| Peak memory | 233176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623006093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3623006093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2067724674 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3053601160 ps |
| CPU time | 6.18 seconds |
| Started | Aug 23 05:14:28 PM UTC 24 |
| Finished | Aug 23 05:14:35 PM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067724674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.2067724674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.3866320607 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1700925044 ps |
| CPU time | 1.63 seconds |
| Started | Aug 23 05:14:28 PM UTC 24 |
| Finished | Aug 23 05:14:31 PM UTC 24 |
| Peak memory | 215436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866320607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3866320607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3777665826 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2852763459 ps |
| CPU time | 6.43 seconds |
| Started | Aug 23 05:14:30 PM UTC 24 |
| Finished | Aug 23 05:14:38 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777665826 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3777665826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.422455111 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 186907039 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 05:14:32 PM UTC 24 |
| Finished | Aug 23 05:14:34 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422455111 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.422455111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.3685188093 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 864303668 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 05:14:32 PM UTC 24 |
| Finished | Aug 23 05:14:35 PM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685188093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3685188093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3111766377 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 7649116146 ps |
| CPU time | 20.88 seconds |
| Started | Aug 23 05:14:32 PM UTC 24 |
| Finished | Aug 23 05:14:54 PM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111766377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.3111766377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3091562212 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4180914522 ps |
| CPU time | 4.95 seconds |
| Started | Aug 23 05:14:30 PM UTC 24 |
| Finished | Aug 23 05:14:36 PM UTC 24 |
| Peak memory | 226640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091562212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3091562212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1800347733 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6841318814 ps |
| CPU time | 9.83 seconds |
| Started | Aug 23 05:14:32 PM UTC 24 |
| Finished | Aug 23 05:14:43 PM UTC 24 |
| Peak memory | 216328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800347733 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1800347733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1760568272 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 75271650 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:14:34 PM UTC 24 |
| Finished | Aug 23 05:14:36 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760568272 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1760568272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3441194050 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 60746123703 ps |
| CPU time | 170.43 seconds |
| Started | Aug 23 05:14:33 PM UTC 24 |
| Finished | Aug 23 05:17:26 PM UTC 24 |
| Peak memory | 226688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441194050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3441194050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2335319842 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 5275025681 ps |
| CPU time | 6.95 seconds |
| Started | Aug 23 05:14:32 PM UTC 24 |
| Finished | Aug 23 05:14:40 PM UTC 24 |
| Peak memory | 216308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335319842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2335319842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.913438179 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 5450005304 ps |
| CPU time | 4.91 seconds |
| Started | Aug 23 05:14:32 PM UTC 24 |
| Finished | Aug 23 05:14:38 PM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913438179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.913438179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3568548531 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 1044901986 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 05:14:32 PM UTC 24 |
| Finished | Aug 23 05:14:35 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568548531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3568548531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.964427957 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 5777622310 ps |
| CPU time | 8.14 seconds |
| Started | Aug 23 05:14:34 PM UTC 24 |
| Finished | Aug 23 05:14:44 PM UTC 24 |
| Peak memory | 216084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964427957 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.964427957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.753496126 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 151901468 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 05:14:38 PM UTC 24 |
| Finished | Aug 23 05:14:40 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753496126 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.753496126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3691819318 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 13975690041 ps |
| CPU time | 15.86 seconds |
| Started | Aug 23 05:14:37 PM UTC 24 |
| Finished | Aug 23 05:14:54 PM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691819318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3691819318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3492132719 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2644619039 ps |
| CPU time | 5.92 seconds |
| Started | Aug 23 05:14:36 PM UTC 24 |
| Finished | Aug 23 05:14:43 PM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492132719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3492132719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.83234077 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1131829780 ps |
| CPU time | 4.2 seconds |
| Started | Aug 23 05:14:35 PM UTC 24 |
| Finished | Aug 23 05:14:41 PM UTC 24 |
| Peak memory | 216272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83234077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.83234077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2686345363 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2004776524 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 05:14:35 PM UTC 24 |
| Finished | Aug 23 05:14:38 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686345363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2686345363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.149026399 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1697780974 ps |
| CPU time | 4.09 seconds |
| Started | Aug 23 05:14:37 PM UTC 24 |
| Finished | Aug 23 05:14:42 PM UTC 24 |
| Peak memory | 226188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149026399 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.149026399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.2061456573 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 104004103 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 05:14:41 PM UTC 24 |
| Finished | Aug 23 05:14:43 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061456573 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2061456573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3699086747 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1717710861 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 05:14:39 PM UTC 24 |
| Finished | Aug 23 05:14:43 PM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699086747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3699086747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2131521716 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2957181750 ps |
| CPU time | 8.94 seconds |
| Started | Aug 23 05:14:39 PM UTC 24 |
| Finished | Aug 23 05:14:49 PM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131521716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.2131521716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2764866748 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3251225306 ps |
| CPU time | 4.78 seconds |
| Started | Aug 23 05:14:38 PM UTC 24 |
| Finished | Aug 23 05:14:43 PM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764866748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2764866748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2172931031 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 55835104 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 05:14:43 PM UTC 24 |
| Finished | Aug 23 05:14:45 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172931031 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2172931031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4190177162 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 14244609528 ps |
| CPU time | 33.82 seconds |
| Started | Aug 23 05:14:43 PM UTC 24 |
| Finished | Aug 23 05:15:18 PM UTC 24 |
| Peak memory | 228532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190177162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4190177162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3180465659 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1294460307 ps |
| CPU time | 4.14 seconds |
| Started | Aug 23 05:14:42 PM UTC 24 |
| Finished | Aug 23 05:14:47 PM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180465659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3180465659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2680360328 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 7035063652 ps |
| CPU time | 16.49 seconds |
| Started | Aug 23 05:14:42 PM UTC 24 |
| Finished | Aug 23 05:15:00 PM UTC 24 |
| Peak memory | 216204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680360328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.2680360328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.2910136808 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 773631452 ps |
| CPU time | 1.24 seconds |
| Started | Aug 23 05:14:42 PM UTC 24 |
| Finished | Aug 23 05:14:44 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910136808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2910136808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.441062857 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3180759795 ps |
| CPU time | 9.44 seconds |
| Started | Aug 23 05:14:43 PM UTC 24 |
| Finished | Aug 23 05:14:54 PM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441062857 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.441062857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1568789178 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 59721955 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 05:14:45 PM UTC 24 |
| Finished | Aug 23 05:14:47 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568789178 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1568789178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.844081173 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3118841518 ps |
| CPU time | 3.51 seconds |
| Started | Aug 23 05:14:44 PM UTC 24 |
| Finished | Aug 23 05:14:49 PM UTC 24 |
| Peak memory | 233352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844081173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.844081173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.2618794423 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3140530534 ps |
| CPU time | 5.82 seconds |
| Started | Aug 23 05:14:44 PM UTC 24 |
| Finished | Aug 23 05:14:51 PM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618794423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2618794423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3674923391 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5952053420 ps |
| CPU time | 4.94 seconds |
| Started | Aug 23 05:14:44 PM UTC 24 |
| Finished | Aug 23 05:14:50 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674923391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.3674923391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.1017940327 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1813013289 ps |
| CPU time | 5.8 seconds |
| Started | Aug 23 05:14:44 PM UTC 24 |
| Finished | Aug 23 05:14:51 PM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017940327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1017940327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.4090219552 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 5774541639 ps |
| CPU time | 5.56 seconds |
| Started | Aug 23 05:14:44 PM UTC 24 |
| Finished | Aug 23 05:14:51 PM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090219552 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.4090219552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1231805837 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 45487604 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 05:14:50 PM UTC 24 |
| Finished | Aug 23 05:14:51 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231805837 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1231805837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.2866307408 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 22125158203 ps |
| CPU time | 20.19 seconds |
| Started | Aug 23 05:14:48 PM UTC 24 |
| Finished | Aug 23 05:15:09 PM UTC 24 |
| Peak memory | 228476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866307408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2866307408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1847402084 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 6200964139 ps |
| CPU time | 5.5 seconds |
| Started | Aug 23 05:14:48 PM UTC 24 |
| Finished | Aug 23 05:14:54 PM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847402084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1847402084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1858011144 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 14270391045 ps |
| CPU time | 22.72 seconds |
| Started | Aug 23 05:14:48 PM UTC 24 |
| Finished | Aug 23 05:15:11 PM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858011144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.1858011144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.686430660 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3191153553 ps |
| CPU time | 10.09 seconds |
| Started | Aug 23 05:14:45 PM UTC 24 |
| Finished | Aug 23 05:14:57 PM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686430660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.686430660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2794823643 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 6282931825 ps |
| CPU time | 5.83 seconds |
| Started | Aug 23 05:14:49 PM UTC 24 |
| Finished | Aug 23 05:14:56 PM UTC 24 |
| Peak memory | 215992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794823643 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2794823643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1133732682 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 46654952 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 05:14:52 PM UTC 24 |
| Finished | Aug 23 05:14:54 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133732682 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1133732682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1928654405 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 10616615410 ps |
| CPU time | 31.55 seconds |
| Started | Aug 23 05:14:52 PM UTC 24 |
| Finished | Aug 23 05:15:25 PM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928654405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1928654405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2555742699 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4859304496 ps |
| CPU time | 3.84 seconds |
| Started | Aug 23 05:14:51 PM UTC 24 |
| Finished | Aug 23 05:14:56 PM UTC 24 |
| Peak memory | 216252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555742699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2555742699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2553943302 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3165562792 ps |
| CPU time | 3.32 seconds |
| Started | Aug 23 05:14:50 PM UTC 24 |
| Finished | Aug 23 05:14:54 PM UTC 24 |
| Peak memory | 226688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553943302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.2553943302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1124478019 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 2149080013 ps |
| CPU time | 1.6 seconds |
| Started | Aug 23 05:14:50 PM UTC 24 |
| Finished | Aug 23 05:14:52 PM UTC 24 |
| Peak memory | 215548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124478019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1124478019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.3545738945 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4054184460 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 05:14:52 PM UTC 24 |
| Finished | Aug 23 05:14:56 PM UTC 24 |
| Peak memory | 216064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545738945 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3545738945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.27336241 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 75353297 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 05:13:54 PM UTC 24 |
| Finished | Aug 23 05:13:55 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27336241 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.27336241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.459279023 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1101422669 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 05:13:51 PM UTC 24 |
| Finished | Aug 23 05:13:56 PM UTC 24 |
| Peak memory | 216216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459279023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.459279023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.1312909034 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 414472870 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 05:13:52 PM UTC 24 |
| Finished | Aug 23 05:13:55 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312909034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.1312909034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.257919965 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4212244809 ps |
| CPU time | 4.08 seconds |
| Started | Aug 23 05:13:51 PM UTC 24 |
| Finished | Aug 23 05:13:57 PM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257919965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.257919965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2749097132 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 379427851 ps |
| CPU time | 1.09 seconds |
| Started | Aug 23 05:13:52 PM UTC 24 |
| Finished | Aug 23 05:13:55 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749097132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.2749097132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3915206197 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 86035712 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 05:13:52 PM UTC 24 |
| Finished | Aug 23 05:13:54 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915206197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3915206197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3600057123 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 5233597101 ps |
| CPU time | 2.13 seconds |
| Started | Aug 23 05:13:51 PM UTC 24 |
| Finished | Aug 23 05:13:55 PM UTC 24 |
| Peak memory | 226556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600057123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3600057123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1036029174 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1303860968 ps |
| CPU time | 4.18 seconds |
| Started | Aug 23 05:13:54 PM UTC 24 |
| Finished | Aug 23 05:13:59 PM UTC 24 |
| Peak memory | 254564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036029174 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1036029174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3266546420 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 65943791 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 05:13:52 PM UTC 24 |
| Finished | Aug 23 05:13:54 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266546420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.3266546420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.3989022686 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4823387699 ps |
| CPU time | 5.53 seconds |
| Started | Aug 23 05:13:52 PM UTC 24 |
| Finished | Aug 23 05:13:59 PM UTC 24 |
| Peak memory | 226508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989022686 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3989022686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/2.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.261557721 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 36335183 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:14:53 PM UTC 24 |
| Finished | Aug 23 05:14:55 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261557721 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.261557721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.1188893672 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1787778735 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 05:14:52 PM UTC 24 |
| Finished | Aug 23 05:14:55 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188893672 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1188893672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1084641042 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 86009660 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:14:54 PM UTC 24 |
| Finished | Aug 23 05:14:56 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084641042 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1084641042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.1842498908 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3529126272 ps |
| CPU time | 6.23 seconds |
| Started | Aug 23 05:14:54 PM UTC 24 |
| Finished | Aug 23 05:15:01 PM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842498908 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1842498908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.1191542326 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 118811320 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 05:14:55 PM UTC 24 |
| Finished | Aug 23 05:14:57 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191542326 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1191542326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2571056139 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2457247983 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 05:14:54 PM UTC 24 |
| Finished | Aug 23 05:14:58 PM UTC 24 |
| Peak memory | 226356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571056139 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2571056139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.354345144 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 79674302 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 05:14:55 PM UTC 24 |
| Finished | Aug 23 05:14:57 PM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354345144 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.354345144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.1390915983 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5059277043 ps |
| CPU time | 4.56 seconds |
| Started | Aug 23 05:14:55 PM UTC 24 |
| Finished | Aug 23 05:15:01 PM UTC 24 |
| Peak memory | 216212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390915983 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1390915983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.974850420 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 76588032 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:14:55 PM UTC 24 |
| Finished | Aug 23 05:14:57 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974850420 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.974850420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.530370814 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4602419074 ps |
| CPU time | 13.1 seconds |
| Started | Aug 23 05:14:55 PM UTC 24 |
| Finished | Aug 23 05:15:10 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530370814 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.530370814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.4012680669 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 115257456 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:14:56 PM UTC 24 |
| Finished | Aug 23 05:14:58 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012680669 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4012680669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.694533497 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 38545722 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:14:57 PM UTC 24 |
| Finished | Aug 23 05:14:58 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694533497 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.694533497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3586256200 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5115831754 ps |
| CPU time | 12.38 seconds |
| Started | Aug 23 05:14:56 PM UTC 24 |
| Finished | Aug 23 05:15:10 PM UTC 24 |
| Peak memory | 226296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586256200 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3586256200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.515459473 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 85050782 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 05:14:58 PM UTC 24 |
| Finished | Aug 23 05:14:59 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515459473 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.515459473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2456571598 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 765027130 ps |
| CPU time | 2.88 seconds |
| Started | Aug 23 05:14:58 PM UTC 24 |
| Finished | Aug 23 05:15:02 PM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456571598 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2456571598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3369411688 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 93829875 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 05:14:58 PM UTC 24 |
| Finished | Aug 23 05:14:59 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369411688 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3369411688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.3963756051 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2997141589 ps |
| CPU time | 1.34 seconds |
| Started | Aug 23 05:14:58 PM UTC 24 |
| Finished | Aug 23 05:15:00 PM UTC 24 |
| Peak memory | 215188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963756051 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.3963756051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.4192933210 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 47925414 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 05:14:59 PM UTC 24 |
| Finished | Aug 23 05:15:00 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192933210 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.4192933210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1294506708 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4566535253 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 05:14:59 PM UTC 24 |
| Finished | Aug 23 05:15:04 PM UTC 24 |
| Peak memory | 216048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294506708 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1294506708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/29.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3496617822 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 98780785 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:13:57 PM UTC 24 |
| Finished | Aug 23 05:13:59 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496617822 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3496617822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2464834821 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 29746633273 ps |
| CPU time | 24.91 seconds |
| Started | Aug 23 05:13:55 PM UTC 24 |
| Finished | Aug 23 05:14:21 PM UTC 24 |
| Peak memory | 226628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464834821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2464834821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3291684524 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4151606800 ps |
| CPU time | 7.2 seconds |
| Started | Aug 23 05:13:55 PM UTC 24 |
| Finished | Aug 23 05:14:03 PM UTC 24 |
| Peak memory | 226576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291684524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3291684524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1200482434 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3587421458 ps |
| CPU time | 6.4 seconds |
| Started | Aug 23 05:13:55 PM UTC 24 |
| Finished | Aug 23 05:14:02 PM UTC 24 |
| Peak memory | 216316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200482434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.1200482434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.4038547740 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1363639514 ps |
| CPU time | 1.63 seconds |
| Started | Aug 23 05:13:56 PM UTC 24 |
| Finished | Aug 23 05:13:58 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038547740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.4038547740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1585530490 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 93049084 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 05:13:55 PM UTC 24 |
| Finished | Aug 23 05:13:57 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585530490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1585530490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1583945146 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 10505086961 ps |
| CPU time | 11.7 seconds |
| Started | Aug 23 05:13:54 PM UTC 24 |
| Finished | Aug 23 05:14:07 PM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583945146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1583945146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.966683636 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 438718463 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 05:13:56 PM UTC 24 |
| Finished | Aug 23 05:13:59 PM UTC 24 |
| Peak memory | 254724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966683636 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.966683636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1377772903 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 70121887 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 05:13:56 PM UTC 24 |
| Finished | Aug 23 05:13:58 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377772903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.1377772903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2408974986 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7777781794 ps |
| CPU time | 6.51 seconds |
| Started | Aug 23 05:13:56 PM UTC 24 |
| Finished | Aug 23 05:14:04 PM UTC 24 |
| Peak memory | 216152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408974986 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2408974986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.1378020745 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 7474816346 ps |
| CPU time | 51.67 seconds |
| Started | Aug 23 05:13:56 PM UTC 24 |
| Finished | Aug 23 05:14:49 PM UTC 24 |
| Peak memory | 242452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1378020745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres s_all_with_rand_reset.1378020745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2907756648 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 86004865 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 05:14:59 PM UTC 24 |
| Finished | Aug 23 05:15:00 PM UTC 24 |
| Peak memory | 215064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907756648 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2907756648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1098850617 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2219218544 ps |
| CPU time | 6.45 seconds |
| Started | Aug 23 05:14:59 PM UTC 24 |
| Finished | Aug 23 05:15:06 PM UTC 24 |
| Peak memory | 215948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098850617 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1098850617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.4045962290 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 99190655 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 05:15:00 PM UTC 24 |
| Finished | Aug 23 05:15:02 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045962290 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.4045962290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3281044110 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 53646784 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:15:01 PM UTC 24 |
| Finished | Aug 23 05:15:03 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281044110 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3281044110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3058821448 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2669564753 ps |
| CPU time | 4.48 seconds |
| Started | Aug 23 05:15:01 PM UTC 24 |
| Finished | Aug 23 05:15:07 PM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058821448 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3058821448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1486607026 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 211463407 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 05:15:01 PM UTC 24 |
| Finished | Aug 23 05:15:03 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486607026 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1486607026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3808807477 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 246680004 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 05:15:02 PM UTC 24 |
| Finished | Aug 23 05:15:04 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808807477 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3808807477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2827481929 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1750370437 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 05:15:01 PM UTC 24 |
| Finished | Aug 23 05:15:06 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827481929 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2827481929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1709714042 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 155125586 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 05:15:02 PM UTC 24 |
| Finished | Aug 23 05:15:04 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709714042 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1709714042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.2625620015 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 13973385726 ps |
| CPU time | 20.07 seconds |
| Started | Aug 23 05:15:02 PM UTC 24 |
| Finished | Aug 23 05:15:23 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625620015 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2625620015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2687422137 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 39212713 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:15:03 PM UTC 24 |
| Finished | Aug 23 05:15:05 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687422137 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2687422137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.1213126381 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4578509275 ps |
| CPU time | 6.31 seconds |
| Started | Aug 23 05:15:02 PM UTC 24 |
| Finished | Aug 23 05:15:10 PM UTC 24 |
| Peak memory | 226444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213126381 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1213126381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.4074057832 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 56143554 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 05:15:03 PM UTC 24 |
| Finished | Aug 23 05:15:05 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074057832 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.4074057832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.2371479685 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 7014023766 ps |
| CPU time | 5.6 seconds |
| Started | Aug 23 05:15:03 PM UTC 24 |
| Finished | Aug 23 05:15:10 PM UTC 24 |
| Peak memory | 226232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371479685 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2371479685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.2867249563 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 50163290 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:15:03 PM UTC 24 |
| Finished | Aug 23 05:15:05 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867249563 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2867249563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.249848553 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 6392410272 ps |
| CPU time | 17.39 seconds |
| Started | Aug 23 05:15:03 PM UTC 24 |
| Finished | Aug 23 05:15:22 PM UTC 24 |
| Peak memory | 226248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249848553 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.249848553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1101605201 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 128695254 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 05:15:05 PM UTC 24 |
| Finished | Aug 23 05:15:06 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101605201 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1101605201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.365748023 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2721621815 ps |
| CPU time | 4.51 seconds |
| Started | Aug 23 05:15:05 PM UTC 24 |
| Finished | Aug 23 05:15:10 PM UTC 24 |
| Peak memory | 216140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365748023 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.365748023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.228090742 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 84379755 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 05:14:00 PM UTC 24 |
| Finished | Aug 23 05:14:02 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228090742 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.228090742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.3443303791 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 47337669434 ps |
| CPU time | 70.93 seconds |
| Started | Aug 23 05:13:58 PM UTC 24 |
| Finished | Aug 23 05:15:11 PM UTC 24 |
| Peak memory | 226552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443303791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3443303791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.3926527538 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 9441605671 ps |
| CPU time | 25.65 seconds |
| Started | Aug 23 05:13:58 PM UTC 24 |
| Finished | Aug 23 05:14:25 PM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926527538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3926527538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.138509034 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 126259075 ps |
| CPU time | 1.09 seconds |
| Started | Aug 23 05:13:59 PM UTC 24 |
| Finished | Aug 23 05:14:01 PM UTC 24 |
| Peak memory | 244528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138509034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.138509034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1904240952 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1646816342 ps |
| CPU time | 5.25 seconds |
| Started | Aug 23 05:13:57 PM UTC 24 |
| Finished | Aug 23 05:14:03 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904240952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.1904240952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2973127804 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 763087313 ps |
| CPU time | 2.73 seconds |
| Started | Aug 23 05:13:59 PM UTC 24 |
| Finished | Aug 23 05:14:03 PM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973127804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.2973127804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2956124453 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 126675567 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:13:59 PM UTC 24 |
| Finished | Aug 23 05:14:01 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956124453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2956124453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.798043739 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1849905418 ps |
| CPU time | 2.33 seconds |
| Started | Aug 23 05:13:57 PM UTC 24 |
| Finished | Aug 23 05:14:00 PM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798043739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.798043739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1737594358 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 600061936 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 05:14:00 PM UTC 24 |
| Finished | Aug 23 05:14:04 PM UTC 24 |
| Peak memory | 254840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737594358 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1737594358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2553983732 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1515409089 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 05:14:00 PM UTC 24 |
| Finished | Aug 23 05:14:03 PM UTC 24 |
| Peak memory | 215944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553983732 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2553983732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.3035890158 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 90775259 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:15:05 PM UTC 24 |
| Finished | Aug 23 05:15:06 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035890158 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3035890158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2293985396 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1856699354 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 05:15:05 PM UTC 24 |
| Finished | Aug 23 05:15:08 PM UTC 24 |
| Peak memory | 226368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293985396 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2293985396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.277652141 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 114634675 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:15:06 PM UTC 24 |
| Finished | Aug 23 05:15:08 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277652141 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.277652141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.931327215 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1253389146 ps |
| CPU time | 2.24 seconds |
| Started | Aug 23 05:15:06 PM UTC 24 |
| Finished | Aug 23 05:15:09 PM UTC 24 |
| Peak memory | 216040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931327215 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.931327215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1958254297 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 100572314 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:15:06 PM UTC 24 |
| Finished | Aug 23 05:15:08 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958254297 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1958254297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.1184872812 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3585494315 ps |
| CPU time | 4.92 seconds |
| Started | Aug 23 05:15:06 PM UTC 24 |
| Finished | Aug 23 05:15:12 PM UTC 24 |
| Peak memory | 216200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184872812 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1184872812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.705203585 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 39798662 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 05:15:07 PM UTC 24 |
| Finished | Aug 23 05:15:09 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705203585 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.705203585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.2249168136 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3355512672 ps |
| CPU time | 5.47 seconds |
| Started | Aug 23 05:15:07 PM UTC 24 |
| Finished | Aug 23 05:15:14 PM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249168136 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2249168136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.614432083 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 86919201 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 05:15:07 PM UTC 24 |
| Finished | Aug 23 05:15:09 PM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614432083 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.614432083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.144492835 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2823164613 ps |
| CPU time | 4.99 seconds |
| Started | Aug 23 05:15:07 PM UTC 24 |
| Finished | Aug 23 05:15:13 PM UTC 24 |
| Peak memory | 216208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144492835 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.144492835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.1962816241 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 32771680 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 05:15:08 PM UTC 24 |
| Finished | Aug 23 05:15:10 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962816241 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1962816241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3171508318 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1670534834 ps |
| CPU time | 5.52 seconds |
| Started | Aug 23 05:15:07 PM UTC 24 |
| Finished | Aug 23 05:15:14 PM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171508318 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3171508318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3709743209 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 51566667 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 05:15:10 PM UTC 24 |
| Finished | Aug 23 05:15:11 PM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709743209 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3709743209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.1318310268 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4237499541 ps |
| CPU time | 4.32 seconds |
| Started | Aug 23 05:15:08 PM UTC 24 |
| Finished | Aug 23 05:15:14 PM UTC 24 |
| Peak memory | 216120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318310268 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1318310268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.864971963 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 146660268 ps |
| CPU time | 0.88 seconds |
| Started | Aug 23 05:15:10 PM UTC 24 |
| Finished | Aug 23 05:15:12 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864971963 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.864971963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.18034849 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2149715309 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 05:15:10 PM UTC 24 |
| Finished | Aug 23 05:15:13 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18034849 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.18034849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2958504022 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 70033125 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 05:15:10 PM UTC 24 |
| Finished | Aug 23 05:15:11 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958504022 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2958504022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.1850748103 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2125909582 ps |
| CPU time | 5.99 seconds |
| Started | Aug 23 05:15:10 PM UTC 24 |
| Finished | Aug 23 05:15:17 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850748103 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1850748103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/48.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.3545906796 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 53719405 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:15:11 PM UTC 24 |
| Finished | Aug 23 05:15:13 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545906796 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3545906796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.567922768 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8733013327 ps |
| CPU time | 9.01 seconds |
| Started | Aug 23 05:15:11 PM UTC 24 |
| Finished | Aug 23 05:15:21 PM UTC 24 |
| Peak memory | 226312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567922768 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.567922768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2136623023 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 45628250 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:14:04 PM UTC 24 |
| Finished | Aug 23 05:14:06 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136623023 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2136623023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1736566890 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 6194566980 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 05:14:03 PM UTC 24 |
| Finished | Aug 23 05:14:08 PM UTC 24 |
| Peak memory | 216260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736566890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1736566890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.170604493 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 309596031 ps |
| CPU time | 1.13 seconds |
| Started | Aug 23 05:14:03 PM UTC 24 |
| Finished | Aug 23 05:14:05 PM UTC 24 |
| Peak memory | 257836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170604493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.170604493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.960218982 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1652489621 ps |
| CPU time | 2.01 seconds |
| Started | Aug 23 05:14:02 PM UTC 24 |
| Finished | Aug 23 05:14:05 PM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960218982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.960218982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3503903223 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 515171605 ps |
| CPU time | 2.13 seconds |
| Started | Aug 23 05:14:03 PM UTC 24 |
| Finished | Aug 23 05:14:06 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503903223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3503903223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3323630107 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 819765824 ps |
| CPU time | 1.36 seconds |
| Started | Aug 23 05:14:02 PM UTC 24 |
| Finished | Aug 23 05:14:04 PM UTC 24 |
| Peak memory | 215496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323630107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3323630107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1812653213 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3244815202 ps |
| CPU time | 9.91 seconds |
| Started | Aug 23 05:14:04 PM UTC 24 |
| Finished | Aug 23 05:14:15 PM UTC 24 |
| Peak memory | 226308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812653213 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1812653213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.704117121 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 57576027 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 05:14:06 PM UTC 24 |
| Finished | Aug 23 05:14:08 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704117121 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.704117121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2426683441 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3193023776 ps |
| CPU time | 3.57 seconds |
| Started | Aug 23 05:14:05 PM UTC 24 |
| Finished | Aug 23 05:14:10 PM UTC 24 |
| Peak memory | 226616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426683441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2426683441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2716770408 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 940310541 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 05:14:05 PM UTC 24 |
| Finished | Aug 23 05:14:07 PM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716770408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2716770408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.3819945882 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 121648658 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 05:14:05 PM UTC 24 |
| Finished | Aug 23 05:14:07 PM UTC 24 |
| Peak memory | 252296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819945882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_buffered_enable.3819945882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2171124158 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5729910970 ps |
| CPU time | 4.23 seconds |
| Started | Aug 23 05:14:04 PM UTC 24 |
| Finished | Aug 23 05:14:09 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171124158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.2171124158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.754616496 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 679026194 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 05:14:05 PM UTC 24 |
| Finished | Aug 23 05:14:07 PM UTC 24 |
| Peak memory | 213396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754616496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.754616496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3698776112 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 8208331229 ps |
| CPU time | 23.49 seconds |
| Started | Aug 23 05:14:04 PM UTC 24 |
| Finished | Aug 23 05:14:29 PM UTC 24 |
| Peak memory | 216340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698776112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3698776112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.3513572205 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4784404679 ps |
| CPU time | 2.39 seconds |
| Started | Aug 23 05:14:06 PM UTC 24 |
| Finished | Aug 23 05:14:10 PM UTC 24 |
| Peak memory | 216088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513572205 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3513572205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/6.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1246707490 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 51403081 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:14:11 PM UTC 24 |
| Finished | Aug 23 05:14:12 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246707490 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1246707490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.185148419 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 21058435854 ps |
| CPU time | 17.4 seconds |
| Started | Aug 23 05:14:08 PM UTC 24 |
| Finished | Aug 23 05:14:27 PM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185148419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.185148419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.2996870616 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1869114931 ps |
| CPU time | 2.36 seconds |
| Started | Aug 23 05:14:08 PM UTC 24 |
| Finished | Aug 23 05:14:12 PM UTC 24 |
| Peak memory | 216188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996870616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2996870616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3721088726 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 311916503 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 05:14:08 PM UTC 24 |
| Finished | Aug 23 05:14:11 PM UTC 24 |
| Peak memory | 257832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721088726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.3721088726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1876556255 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 11607726605 ps |
| CPU time | 16.11 seconds |
| Started | Aug 23 05:14:08 PM UTC 24 |
| Finished | Aug 23 05:14:26 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876556255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.1876556255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.4273361995 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 949127802 ps |
| CPU time | 1.48 seconds |
| Started | Aug 23 05:14:08 PM UTC 24 |
| Finished | Aug 23 05:14:11 PM UTC 24 |
| Peak memory | 213344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273361995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.4273361995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.4262384530 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1859125287 ps |
| CPU time | 2.58 seconds |
| Started | Aug 23 05:14:07 PM UTC 24 |
| Finished | Aug 23 05:14:11 PM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262384530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4262384530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.1538745714 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2337464430 ps |
| CPU time | 3.62 seconds |
| Started | Aug 23 05:14:11 PM UTC 24 |
| Finished | Aug 23 05:14:15 PM UTC 24 |
| Peak memory | 216148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538745714 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1538745714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.3235854063 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 100398521 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 05:14:17 PM UTC 24 |
| Finished | Aug 23 05:14:19 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235854063 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3235854063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.3739153875 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5374233783 ps |
| CPU time | 2.36 seconds |
| Started | Aug 23 05:14:12 PM UTC 24 |
| Finished | Aug 23 05:14:15 PM UTC 24 |
| Peak memory | 226616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739153875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3739153875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3444503173 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4945437242 ps |
| CPU time | 15.37 seconds |
| Started | Aug 23 05:14:12 PM UTC 24 |
| Finished | Aug 23 05:14:28 PM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444503173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3444503173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.943822263 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 236519287 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 05:14:13 PM UTC 24 |
| Finished | Aug 23 05:14:15 PM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943822263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.943822263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1352082810 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 3535061493 ps |
| CPU time | 10.14 seconds |
| Started | Aug 23 05:14:12 PM UTC 24 |
| Finished | Aug 23 05:14:23 PM UTC 24 |
| Peak memory | 216256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352082810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.1352082810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.4152433951 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 7765670031 ps |
| CPU time | 6.85 seconds |
| Started | Aug 23 05:14:11 PM UTC 24 |
| Finished | Aug 23 05:14:19 PM UTC 24 |
| Peak memory | 226560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152433951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.4152433951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.1699922123 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 4279967200 ps |
| CPU time | 12.33 seconds |
| Started | Aug 23 05:14:13 PM UTC 24 |
| Finished | Aug 23 05:14:26 PM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699922123 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1699922123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.2271306597 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 74318759 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 05:14:24 PM UTC 24 |
| Finished | Aug 23 05:14:26 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271306597 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2271306597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2077681128 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1515255842 ps |
| CPU time | 5.24 seconds |
| Started | Aug 23 05:14:18 PM UTC 24 |
| Finished | Aug 23 05:14:24 PM UTC 24 |
| Peak memory | 216248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077681128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2077681128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.1683341019 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3013253158 ps |
| CPU time | 8.15 seconds |
| Started | Aug 23 05:14:17 PM UTC 24 |
| Finished | Aug 23 05:14:26 PM UTC 24 |
| Peak memory | 226568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683341019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1683341019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.706500065 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 242874176 ps |
| CPU time | 0.95 seconds |
| Started | Aug 23 05:14:20 PM UTC 24 |
| Finished | Aug 23 05:14:22 PM UTC 24 |
| Peak memory | 258732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706500065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.706500065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1924630681 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5873546357 ps |
| CPU time | 11.79 seconds |
| Started | Aug 23 05:14:17 PM UTC 24 |
| Finished | Aug 23 05:14:30 PM UTC 24 |
| Peak memory | 216320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924630681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.1924630681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.1493395368 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 4119080426 ps |
| CPU time | 11.7 seconds |
| Started | Aug 23 05:14:17 PM UTC 24 |
| Finished | Aug 23 05:14:30 PM UTC 24 |
| Peak memory | 216456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493395368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1493395368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.262684201 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 1203267009 ps |
| CPU time | 2.21 seconds |
| Started | Aug 23 05:14:20 PM UTC 24 |
| Finished | Aug 23 05:14:23 PM UTC 24 |
| Peak memory | 216024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262684201 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.262684201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.1195386349 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2909820780 ps |
| CPU time | 45.39 seconds |
| Started | Aug 23 05:14:22 PM UTC 24 |
| Finished | Aug 23 05:15:09 PM UTC 24 |
| Peak memory | 243416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1195386349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stres s_all_with_rand_reset.1195386349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |