Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.13 96.32 90.10 92.10 94.67 90.78 98.74 61.18


Total tests in report: 483
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
54.27 54.27 83.88 83.88 49.93 49.93 44.37 44.37 44.00 44.00 62.46 62.46 93.17 93.17 2.06 2.06 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3077061184
64.77 10.51 85.39 1.51 59.41 9.48 47.73 3.36 50.67 6.67 68.26 5.80 94.22 1.05 47.74 45.68 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.204917532
74.68 9.91 89.77 4.38 72.56 13.15 80.55 32.82 57.33 6.67 76.45 8.19 95.37 1.16 50.75 3.02 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2146063647
78.67 3.98 92.85 3.07 76.94 4.38 84.58 4.03 68.00 10.67 81.06 4.61 95.79 0.42 51.44 0.69 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4145732152
80.38 1.72 92.90 0.05 77.65 0.71 85.00 0.42 77.33 9.33 82.42 1.37 95.79 0.00 51.58 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3314365704
81.70 1.32 93.50 0.60 78.93 1.27 87.86 2.86 80.00 2.67 84.13 1.71 95.79 0.00 51.71 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.300156872
82.65 0.94 93.60 0.10 80.48 1.56 88.78 0.92 80.00 0.00 84.64 0.51 96.00 0.21 55.01 3.29 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3076555197
83.47 0.82 94.26 0.65 81.47 0.99 89.37 0.59 82.67 2.67 85.49 0.85 96.00 0.00 55.01 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.3781405515
84.08 0.61 95.01 0.76 82.32 0.85 89.37 0.00 84.00 1.33 86.69 1.19 96.00 0.00 55.14 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2879649011
84.65 0.57 95.01 0.00 82.32 0.00 89.37 0.00 88.00 4.00 86.69 0.00 96.00 0.00 55.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1724299111
85.08 0.43 95.06 0.05 83.03 0.71 89.96 0.59 89.33 1.33 86.86 0.17 96.00 0.00 55.28 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.63265529
85.46 0.38 95.06 0.00 83.03 0.00 89.96 0.00 92.00 2.67 86.86 0.00 96.00 0.00 55.28 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.4125865351
85.83 0.37 95.47 0.40 84.30 1.27 90.04 0.08 92.00 0.00 87.71 0.85 96.00 0.00 55.28 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3271429971
86.15 0.32 95.47 0.00 86.56 2.26 90.04 0.00 92.00 0.00 87.71 0.00 96.00 0.00 55.28 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.626581748
86.47 0.32 95.72 0.25 87.13 0.57 90.38 0.34 92.00 0.00 88.23 0.51 96.00 0.00 55.83 0.55 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2058990339
86.75 0.28 95.72 0.00 87.55 0.42 91.13 0.76 92.00 0.00 88.23 0.00 96.11 0.11 56.52 0.69 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1897359304
87.02 0.27 95.87 0.15 87.69 0.14 91.22 0.08 93.33 1.33 88.40 0.17 96.11 0.00 56.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3992817678
87.24 0.22 96.12 0.25 87.84 0.14 91.26 0.04 93.33 0.00 89.42 1.02 96.21 0.11 56.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1159027491
87.45 0.20 96.12 0.00 87.84 0.00 91.34 0.08 94.67 1.33 89.42 0.00 96.21 0.00 56.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4063395800
87.63 0.18 96.12 0.00 87.84 0.00 91.34 0.00 94.67 0.00 89.42 0.00 97.48 1.26 56.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3125658771
87.79 0.16 96.17 0.05 88.26 0.42 91.47 0.13 94.67 0.00 89.42 0.00 97.48 0.00 57.06 0.55 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2886847246
87.94 0.15 96.17 0.00 89.11 0.85 91.55 0.08 94.67 0.00 89.42 0.00 97.58 0.11 57.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.3804051963
88.06 0.12 96.17 0.00 89.11 0.00 91.55 0.00 94.67 0.00 89.42 0.00 97.58 0.00 57.89 0.82 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.4140928122
88.17 0.11 96.17 0.00 89.53 0.42 91.55 0.00 94.67 0.00 89.76 0.34 97.58 0.00 57.89 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.3902964274
88.26 0.10 96.17 0.00 89.53 0.00 91.55 0.00 94.67 0.00 89.76 0.00 97.58 0.00 58.57 0.69 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1998297157
88.35 0.09 96.17 0.00 89.53 0.00 91.55 0.00 94.67 0.00 89.76 0.00 98.21 0.63 58.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.343499826
88.44 0.08 96.22 0.05 89.67 0.14 91.60 0.04 94.67 0.00 90.10 0.34 98.21 0.00 58.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2445522025
88.51 0.08 96.27 0.05 89.82 0.14 91.60 0.00 94.67 0.00 90.44 0.34 98.21 0.00 58.57 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2002757037
88.58 0.07 96.27 0.00 89.82 0.00 91.68 0.08 94.67 0.00 90.44 0.00 98.21 0.00 58.98 0.41 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.484113392
88.64 0.06 96.27 0.00 89.82 0.00 91.97 0.29 94.67 0.00 90.44 0.00 98.21 0.00 59.12 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.514979896
88.70 0.06 96.27 0.00 89.82 0.00 91.97 0.00 94.67 0.00 90.44 0.00 98.21 0.00 59.53 0.41 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3748485722
88.76 0.06 96.27 0.00 89.82 0.00 91.97 0.00 94.67 0.00 90.44 0.00 98.21 0.00 59.95 0.41 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.3501250653
88.82 0.06 96.27 0.00 89.82 0.00 91.97 0.00 94.67 0.00 90.44 0.00 98.21 0.00 60.36 0.41 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3012947054
88.86 0.04 96.27 0.00 89.96 0.14 91.97 0.00 94.67 0.00 90.61 0.17 98.21 0.00 60.36 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.1833164334
88.90 0.03 96.27 0.00 89.96 0.00 92.06 0.08 94.67 0.00 90.61 0.00 98.21 0.00 60.49 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.575303831
88.93 0.03 96.32 0.05 89.96 0.00 92.06 0.00 94.67 0.00 90.78 0.17 98.21 0.00 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2439543586
88.96 0.03 96.32 0.00 89.96 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.42 0.21 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4048471174
88.98 0.02 96.32 0.00 90.10 0.14 92.06 0.00 94.67 0.00 90.78 0.00 98.42 0.00 60.49 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3352060927
89.00 0.02 96.32 0.00 90.10 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.42 0.00 60.63 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2170903361
89.02 0.02 96.32 0.00 90.10 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.42 0.00 60.77 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1704309550
89.04 0.02 96.32 0.00 90.10 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.42 0.00 60.91 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4106214083
89.06 0.02 96.32 0.00 90.10 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.42 0.00 61.04 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2628682644
89.08 0.02 96.32 0.00 90.10 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.42 0.00 61.18 0.14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.774458627
89.09 0.02 96.32 0.00 90.10 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.53 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.4244649669
89.11 0.02 96.32 0.00 90.10 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.63 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.363057983
89.12 0.02 96.32 0.00 90.10 0.00 92.06 0.00 94.67 0.00 90.78 0.00 98.74 0.11 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1706039454
89.13 0.01 96.32 0.00 90.10 0.00 92.10 0.04 94.67 0.00 90.78 0.00 98.74 0.00 61.18 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4151702554

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1069953584
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1376487297
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.186338087
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2520327505
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1071296655
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3293452549
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2370266801
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1490232975
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1880619592
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1201369673
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.34782478
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2213515127
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.3504832676
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2636945506
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3818300523
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1442311846
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2149723045
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2631874188
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3781784255
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3512521207
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.455903498
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3401667095
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3636909396
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.693400355
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1903730899
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.568461445
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3048236332
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2599687014
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2262875759
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1183544370
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2413566555
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.3258687687
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3705012785
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.976390520
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3720605856
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.14800555
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1891214538
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1871876298
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.2065642962
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3043172777
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.989886177
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2232634803
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2627620183
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3634398775
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2826216022
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1687489849
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.1331051361
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1187194033
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1931451310
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.1237639480
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/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.2271306597
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/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.1683341019
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/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1924630681
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.1493395368
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.262684201
/workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.1195386349



Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.3077061184 Aug 23 05:13:35 PM UTC 24 Aug 23 05:13:37 PM UTC 24 1019281192 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.139256027 Aug 23 05:13:35 PM UTC 24 Aug 23 05:13:38 PM UTC 24 1198556729 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3391940339 Aug 23 05:13:34 PM UTC 24 Aug 23 05:13:38 PM UTC 24 2089501863 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4093595082 Aug 23 05:13:36 PM UTC 24 Aug 23 05:13:38 PM UTC 24 876648096 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3960237930 Aug 23 05:13:35 PM UTC 24 Aug 23 05:13:38 PM UTC 24 2483436572 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.1159027491 Aug 23 05:13:36 PM UTC 24 Aug 23 05:13:39 PM UTC 24 353079331 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.496359399 Aug 23 05:13:37 PM UTC 24 Aug 23 05:13:39 PM UTC 24 111709948 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.1756304492 Aug 23 05:13:37 PM UTC 24 Aug 23 05:13:39 PM UTC 24 330454339 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.924862839 Aug 23 05:13:36 PM UTC 24 Aug 23 05:13:40 PM UTC 24 783856884 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.859466009 Aug 23 05:13:38 PM UTC 24 Aug 23 05:13:40 PM UTC 24 113921182 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.2213538979 Aug 23 05:13:38 PM UTC 24 Aug 23 05:13:40 PM UTC 24 399497122 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.3352060927 Aug 23 05:13:38 PM UTC 24 Aug 23 05:13:41 PM UTC 24 414739354 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2886847246 Aug 23 05:13:39 PM UTC 24 Aug 23 05:13:41 PM UTC 24 126191928 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.1675963997 Aug 23 05:13:39 PM UTC 24 Aug 23 05:13:42 PM UTC 24 317825648 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3015137184 Aug 23 05:13:39 PM UTC 24 Aug 23 05:13:42 PM UTC 24 270838189 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2146063647 Aug 23 05:13:39 PM UTC 24 Aug 23 05:13:42 PM UTC 24 937113806 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.2445522025 Aug 23 05:13:40 PM UTC 24 Aug 23 05:13:42 PM UTC 24 77176671 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.4151702554 Aug 23 05:13:40 PM UTC 24 Aug 23 05:13:42 PM UTC 24 204165147 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1447849660 Aug 23 05:13:39 PM UTC 24 Aug 23 05:13:42 PM UTC 24 546666351 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.4247476880 Aug 23 05:13:41 PM UTC 24 Aug 23 05:13:42 PM UTC 24 201768018 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.3954840453 Aug 23 05:13:41 PM UTC 24 Aug 23 05:13:43 PM UTC 24 51322005 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.3079981322 Aug 23 05:13:40 PM UTC 24 Aug 23 05:13:43 PM UTC 24 261958591 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2208149632 Aug 23 05:13:39 PM UTC 24 Aug 23 05:13:43 PM UTC 24 1791042201 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.370871958 Aug 23 05:13:39 PM UTC 24 Aug 23 05:13:44 PM UTC 24 2646627046 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.3314365704 Aug 23 05:13:34 PM UTC 24 Aug 23 05:13:44 PM UTC 24 11415825985 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.63265529 Aug 23 05:13:41 PM UTC 24 Aug 23 05:13:44 PM UTC 24 638403234 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1341865059 Aug 23 05:13:42 PM UTC 24 Aug 23 05:13:44 PM UTC 24 273704313 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.626581748 Aug 23 05:13:43 PM UTC 24 Aug 23 05:13:44 PM UTC 24 30118971 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.363057983 Aug 23 05:13:43 PM UTC 24 Aug 23 05:13:45 PM UTC 24 99077888 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.3804051963 Aug 23 05:13:43 PM UTC 24 Aug 23 05:13:45 PM UTC 24 33424902 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1678479861 Aug 23 05:13:43 PM UTC 24 Aug 23 05:13:46 PM UTC 24 1175974885 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.2521766769 Aug 23 05:13:44 PM UTC 24 Aug 23 05:13:47 PM UTC 24 1161280337 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.2609691421 Aug 23 05:13:44 PM UTC 24 Aug 23 05:13:47 PM UTC 24 1293768197 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.199904267 Aug 23 05:13:45 PM UTC 24 Aug 23 05:13:47 PM UTC 24 313143988 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.911360000 Aug 23 05:13:45 PM UTC 24 Aug 23 05:13:47 PM UTC 24 69869107 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.3275579071 Aug 23 05:13:45 PM UTC 24 Aug 23 05:13:47 PM UTC 24 316769063 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.1161341352 Aug 23 05:13:45 PM UTC 24 Aug 23 05:13:47 PM UTC 24 159268865 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.3289000097 Aug 23 05:13:45 PM UTC 24 Aug 23 05:13:48 PM UTC 24 183777213 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.600899970 Aug 23 05:13:45 PM UTC 24 Aug 23 05:13:48 PM UTC 24 873952107 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.4145732152 Aug 23 05:13:43 PM UTC 24 Aug 23 05:13:48 PM UTC 24 7319857977 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2074484361 Aug 23 05:13:44 PM UTC 24 Aug 23 05:13:48 PM UTC 24 2187526553 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2370891256 Aug 23 05:13:45 PM UTC 24 Aug 23 05:13:49 PM UTC 24 621839388 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3802137677 Aug 23 05:13:48 PM UTC 24 Aug 23 05:13:50 PM UTC 24 134392739 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2811368846 Aug 23 05:13:48 PM UTC 24 Aug 23 05:13:50 PM UTC 24 436542766 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.366958012 Aug 23 05:13:45 PM UTC 24 Aug 23 05:13:50 PM UTC 24 1043412964 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3374482253 Aug 23 05:13:48 PM UTC 24 Aug 23 05:13:50 PM UTC 24 130378023 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1865729186 Aug 23 05:13:48 PM UTC 24 Aug 23 05:13:50 PM UTC 24 588321808 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3176731340 Aug 23 05:13:48 PM UTC 24 Aug 23 05:13:50 PM UTC 24 443380181 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.3858822920 Aug 23 05:13:48 PM UTC 24 Aug 23 05:13:50 PM UTC 24 400003726 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.1833164334 Aug 23 05:13:46 PM UTC 24 Aug 23 05:13:50 PM UTC 24 2766805415 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2404054821 Aug 23 05:13:49 PM UTC 24 Aug 23 05:13:51 PM UTC 24 57209709 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.1585452627 Aug 23 05:13:49 PM UTC 24 Aug 23 05:13:51 PM UTC 24 168648958 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2190013737 Aug 23 05:13:49 PM UTC 24 Aug 23 05:13:51 PM UTC 24 161254611 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2595747350 Aug 23 05:13:49 PM UTC 24 Aug 23 05:13:51 PM UTC 24 166367202 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.2832473283 Aug 23 05:13:44 PM UTC 24 Aug 23 05:13:51 PM UTC 24 2020506902 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.2879649011 Aug 23 05:13:49 PM UTC 24 Aug 23 05:13:52 PM UTC 24 229193335 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.1706039454 Aug 23 05:13:50 PM UTC 24 Aug 23 05:13:52 PM UTC 24 139100305 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.2533933824 Aug 23 05:13:44 PM UTC 24 Aug 23 05:13:52 PM UTC 24 4205946096 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.2013673497 Aug 23 05:13:51 PM UTC 24 Aug 23 05:13:53 PM UTC 24 94232224 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.1897359304 Aug 23 05:13:51 PM UTC 24 Aug 23 05:13:54 PM UTC 24 428357334 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3915206197 Aug 23 05:13:52 PM UTC 24 Aug 23 05:13:54 PM UTC 24 86035712 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3266546420 Aug 23 05:13:52 PM UTC 24 Aug 23 05:13:54 PM UTC 24 65943791 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2749097132 Aug 23 05:13:52 PM UTC 24 Aug 23 05:13:55 PM UTC 24 379427851 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3600057123 Aug 23 05:13:51 PM UTC 24 Aug 23 05:13:55 PM UTC 24 5233597101 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.1312909034 Aug 23 05:13:52 PM UTC 24 Aug 23 05:13:55 PM UTC 24 414472870 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.27336241 Aug 23 05:13:54 PM UTC 24 Aug 23 05:13:55 PM UTC 24 75353297 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.459279023 Aug 23 05:13:51 PM UTC 24 Aug 23 05:13:56 PM UTC 24 1101422669 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1585530490 Aug 23 05:13:55 PM UTC 24 Aug 23 05:13:57 PM UTC 24 93049084 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.257919965 Aug 23 05:13:51 PM UTC 24 Aug 23 05:13:57 PM UTC 24 4212244809 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.1377772903 Aug 23 05:13:56 PM UTC 24 Aug 23 05:13:58 PM UTC 24 70121887 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.2002757037 Aug 23 05:13:56 PM UTC 24 Aug 23 05:13:58 PM UTC 24 363537593 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.4038547740 Aug 23 05:13:56 PM UTC 24 Aug 23 05:13:58 PM UTC 24 1363639514 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.3496617822 Aug 23 05:13:57 PM UTC 24 Aug 23 05:13:59 PM UTC 24 98780785 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1036029174 Aug 23 05:13:54 PM UTC 24 Aug 23 05:13:59 PM UTC 24 1303860968 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.3883335853 Aug 23 05:13:44 PM UTC 24 Aug 23 05:13:59 PM UTC 24 8828688597 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.966683636 Aug 23 05:13:56 PM UTC 24 Aug 23 05:13:59 PM UTC 24 438718463 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.3989022686 Aug 23 05:13:52 PM UTC 24 Aug 23 05:13:59 PM UTC 24 4823387699 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.798043739 Aug 23 05:13:57 PM UTC 24 Aug 23 05:14:00 PM UTC 24 1849905418 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.2956124453 Aug 23 05:13:59 PM UTC 24 Aug 23 05:14:01 PM UTC 24 126675567 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.138509034 Aug 23 05:13:59 PM UTC 24 Aug 23 05:14:01 PM UTC 24 126259075 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.228090742 Aug 23 05:14:00 PM UTC 24 Aug 23 05:14:02 PM UTC 24 84379755 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1200482434 Aug 23 05:13:55 PM UTC 24 Aug 23 05:14:02 PM UTC 24 3587421458 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.300156872 Aug 23 05:13:51 PM UTC 24 Aug 23 05:14:03 PM UTC 24 11066108043 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2973127804 Aug 23 05:13:59 PM UTC 24 Aug 23 05:14:03 PM UTC 24 763087313 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3291684524 Aug 23 05:13:55 PM UTC 24 Aug 23 05:14:03 PM UTC 24 4151606800 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.2553983732 Aug 23 05:14:00 PM UTC 24 Aug 23 05:14:03 PM UTC 24 1515409089 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1904240952 Aug 23 05:13:57 PM UTC 24 Aug 23 05:14:03 PM UTC 24 1646816342 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2408974986 Aug 23 05:13:56 PM UTC 24 Aug 23 05:14:04 PM UTC 24 7777781794 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.3323630107 Aug 23 05:14:02 PM UTC 24 Aug 23 05:14:04 PM UTC 24 819765824 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.1737594358 Aug 23 05:14:00 PM UTC 24 Aug 23 05:14:04 PM UTC 24 600061936 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.960218982 Aug 23 05:14:02 PM UTC 24 Aug 23 05:14:05 PM UTC 24 1652489621 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.170604493 Aug 23 05:14:03 PM UTC 24 Aug 23 05:14:05 PM UTC 24 309596031 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2136623023 Aug 23 05:14:04 PM UTC 24 Aug 23 05:14:06 PM UTC 24 45628250 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.3503903223 Aug 23 05:14:03 PM UTC 24 Aug 23 05:14:06 PM UTC 24 515171605 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.1583945146 Aug 23 05:13:54 PM UTC 24 Aug 23 05:14:07 PM UTC 24 10505086961 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_buffered_enable.3819945882 Aug 23 05:14:05 PM UTC 24 Aug 23 05:14:07 PM UTC 24 121648658 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.2716770408 Aug 23 05:14:05 PM UTC 24 Aug 23 05:14:07 PM UTC 24 940310541 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.754616496 Aug 23 05:14:05 PM UTC 24 Aug 23 05:14:07 PM UTC 24 679026194 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.1736566890 Aug 23 05:14:03 PM UTC 24 Aug 23 05:14:08 PM UTC 24 6194566980 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.704117121 Aug 23 05:14:06 PM UTC 24 Aug 23 05:14:08 PM UTC 24 57576027 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2171124158 Aug 23 05:14:04 PM UTC 24 Aug 23 05:14:09 PM UTC 24 5729910970 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.575303831 Aug 23 05:13:50 PM UTC 24 Aug 23 05:14:10 PM UTC 24 7529953485 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.3513572205 Aug 23 05:14:06 PM UTC 24 Aug 23 05:14:10 PM UTC 24 4784404679 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2426683441 Aug 23 05:14:05 PM UTC 24 Aug 23 05:14:10 PM UTC 24 3193023776 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.3721088726 Aug 23 05:14:08 PM UTC 24 Aug 23 05:14:11 PM UTC 24 311916503 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.4262384530 Aug 23 05:14:07 PM UTC 24 Aug 23 05:14:11 PM UTC 24 1859125287 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.4273361995 Aug 23 05:14:08 PM UTC 24 Aug 23 05:14:11 PM UTC 24 949127802 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.2996870616 Aug 23 05:14:08 PM UTC 24 Aug 23 05:14:12 PM UTC 24 1869114931 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.1246707490 Aug 23 05:14:11 PM UTC 24 Aug 23 05:14:12 PM UTC 24 51403081 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.2058990339 Aug 23 05:14:03 PM UTC 24 Aug 23 05:14:14 PM UTC 24 6267504652 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.943822263 Aug 23 05:14:13 PM UTC 24 Aug 23 05:14:15 PM UTC 24 236519287 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.1812653213 Aug 23 05:14:04 PM UTC 24 Aug 23 05:14:15 PM UTC 24 3244815202 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.3739153875 Aug 23 05:14:12 PM UTC 24 Aug 23 05:14:15 PM UTC 24 5374233783 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.1538745714 Aug 23 05:14:11 PM UTC 24 Aug 23 05:14:15 PM UTC 24 2337464430 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.4152433951 Aug 23 05:14:11 PM UTC 24 Aug 23 05:14:19 PM UTC 24 7765670031 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.3235854063 Aug 23 05:14:17 PM UTC 24 Aug 23 05:14:19 PM UTC 24 100398521 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.2464834821 Aug 23 05:13:55 PM UTC 24 Aug 23 05:14:21 PM UTC 24 29746633273 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.706500065 Aug 23 05:14:20 PM UTC 24 Aug 23 05:14:22 PM UTC 24 242874176 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1352082810 Aug 23 05:14:12 PM UTC 24 Aug 23 05:14:23 PM UTC 24 3535061493 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.262684201 Aug 23 05:14:20 PM UTC 24 Aug 23 05:14:23 PM UTC 24 1203267009 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.204917532 Aug 23 05:14:00 PM UTC 24 Aug 23 05:14:24 PM UTC 24 886886067 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2077681128 Aug 23 05:14:18 PM UTC 24 Aug 23 05:14:24 PM UTC 24 1515255842 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.3926527538 Aug 23 05:13:58 PM UTC 24 Aug 23 05:14:25 PM UTC 24 9441605671 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1876556255 Aug 23 05:14:08 PM UTC 24 Aug 23 05:14:26 PM UTC 24 11607726605 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.2271306597 Aug 23 05:14:24 PM UTC 24 Aug 23 05:14:26 PM UTC 24 74318759 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.1699922123 Aug 23 05:14:13 PM UTC 24 Aug 23 05:14:26 PM UTC 24 4279967200 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.1683341019 Aug 23 05:14:17 PM UTC 24 Aug 23 05:14:26 PM UTC 24 3013253158 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.185148419 Aug 23 05:14:08 PM UTC 24 Aug 23 05:14:27 PM UTC 24 21058435854 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3444503173 Aug 23 05:14:12 PM UTC 24 Aug 23 05:14:28 PM UTC 24 4945437242 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.3698776112 Aug 23 05:14:04 PM UTC 24 Aug 23 05:14:29 PM UTC 24 8208331229 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3304163517 Aug 23 05:14:28 PM UTC 24 Aug 23 05:14:30 PM UTC 24 77941361 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.694967383 Aug 23 05:14:26 PM UTC 24 Aug 23 05:14:30 PM UTC 24 3273193186 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.1493395368 Aug 23 05:14:17 PM UTC 24 Aug 23 05:14:30 PM UTC 24 4119080426 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1924630681 Aug 23 05:14:17 PM UTC 24 Aug 23 05:14:30 PM UTC 24 5873546357 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.1662096915 Aug 23 05:13:43 PM UTC 24 Aug 23 05:14:30 PM UTC 24 8232405266 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.1647517374 Aug 23 05:14:26 PM UTC 24 Aug 23 05:14:30 PM UTC 24 2382969394 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.1595793092 Aug 23 05:14:26 PM UTC 24 Aug 23 05:14:30 PM UTC 24 2166629294 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.3866320607 Aug 23 05:14:28 PM UTC 24 Aug 23 05:14:31 PM UTC 24 1700925044 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.487740607 Aug 23 05:14:30 PM UTC 24 Aug 23 05:14:32 PM UTC 24 35160907 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.3623006093 Aug 23 05:14:28 PM UTC 24 Aug 23 05:14:34 PM UTC 24 1360725617 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.422455111 Aug 23 05:14:32 PM UTC 24 Aug 23 05:14:34 PM UTC 24 186907039 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.3568548531 Aug 23 05:14:32 PM UTC 24 Aug 23 05:14:35 PM UTC 24 1044901986 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.3685188093 Aug 23 05:14:32 PM UTC 24 Aug 23 05:14:35 PM UTC 24 864303668 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2067724674 Aug 23 05:14:28 PM UTC 24 Aug 23 05:14:35 PM UTC 24 3053601160 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3091562212 Aug 23 05:14:30 PM UTC 24 Aug 23 05:14:36 PM UTC 24 4180914522 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.1760568272 Aug 23 05:14:34 PM UTC 24 Aug 23 05:14:36 PM UTC 24 75271650 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.3467544614 Aug 23 05:13:51 PM UTC 24 Aug 23 05:14:37 PM UTC 24 4977149037 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3048644321 Aug 23 05:14:24 PM UTC 24 Aug 23 05:14:37 PM UTC 24 7340422785 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3777665826 Aug 23 05:14:30 PM UTC 24 Aug 23 05:14:38 PM UTC 24 2852763459 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2686345363 Aug 23 05:14:35 PM UTC 24 Aug 23 05:14:38 PM UTC 24 2004776524 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.913438179 Aug 23 05:14:32 PM UTC 24 Aug 23 05:14:38 PM UTC 24 5450005304 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.753496126 Aug 23 05:14:38 PM UTC 24 Aug 23 05:14:40 PM UTC 24 151901468 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2335319842 Aug 23 05:14:32 PM UTC 24 Aug 23 05:14:40 PM UTC 24 5275025681 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.83234077 Aug 23 05:14:35 PM UTC 24 Aug 23 05:14:41 PM UTC 24 1131829780 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.514979896 Aug 23 05:14:28 PM UTC 24 Aug 23 05:14:41 PM UTC 24 29719512391 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.149026399 Aug 23 05:14:37 PM UTC 24 Aug 23 05:14:42 PM UTC 24 1697780974 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.4140928122 Aug 23 05:14:32 PM UTC 24 Aug 23 05:14:42 PM UTC 24 3253748185 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3492132719 Aug 23 05:14:36 PM UTC 24 Aug 23 05:14:43 PM UTC 24 2644619039 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.2061456573 Aug 23 05:14:41 PM UTC 24 Aug 23 05:14:43 PM UTC 24 104004103 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.774458627 Aug 23 05:14:40 PM UTC 24 Aug 23 05:14:43 PM UTC 24 1603870939 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.1800347733 Aug 23 05:14:32 PM UTC 24 Aug 23 05:14:43 PM UTC 24 6841318814 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3699086747 Aug 23 05:14:39 PM UTC 24 Aug 23 05:14:43 PM UTC 24 1717710861 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.2764866748 Aug 23 05:14:38 PM UTC 24 Aug 23 05:14:43 PM UTC 24 3251225306 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.964427957 Aug 23 05:14:34 PM UTC 24 Aug 23 05:14:44 PM UTC 24 5777622310 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.2910136808 Aug 23 05:14:42 PM UTC 24 Aug 23 05:14:44 PM UTC 24 773631452 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.2172931031 Aug 23 05:14:43 PM UTC 24 Aug 23 05:14:45 PM UTC 24 55835104 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2628682644 Aug 23 05:14:39 PM UTC 24 Aug 23 05:14:47 PM UTC 24 2214650255 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.2316279008 Aug 23 05:14:26 PM UTC 24 Aug 23 05:14:47 PM UTC 24 9073852219 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.1568789178 Aug 23 05:14:45 PM UTC 24 Aug 23 05:14:47 PM UTC 24 59721955 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3180465659 Aug 23 05:14:42 PM UTC 24 Aug 23 05:14:47 PM UTC 24 1294460307 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2131521716 Aug 23 05:14:39 PM UTC 24 Aug 23 05:14:49 PM UTC 24 2957181750 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.844081173 Aug 23 05:14:44 PM UTC 24 Aug 23 05:14:49 PM UTC 24 3118841518 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.1378020745 Aug 23 05:13:56 PM UTC 24 Aug 23 05:14:49 PM UTC 24 7474816346 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3674923391 Aug 23 05:14:44 PM UTC 24 Aug 23 05:14:50 PM UTC 24 5952053420 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.4090219552 Aug 23 05:14:44 PM UTC 24 Aug 23 05:14:51 PM UTC 24 5774541639 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.1017940327 Aug 23 05:14:44 PM UTC 24 Aug 23 05:14:51 PM UTC 24 1813013289 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.2618794423 Aug 23 05:14:44 PM UTC 24 Aug 23 05:14:51 PM UTC 24 3140530534 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.1231805837 Aug 23 05:14:50 PM UTC 24 Aug 23 05:14:51 PM UTC 24 45487604 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1124478019 Aug 23 05:14:50 PM UTC 24 Aug 23 05:14:52 PM UTC 24 2149080013 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.1133732682 Aug 23 05:14:52 PM UTC 24 Aug 23 05:14:54 PM UTC 24 46654952 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.3691819318 Aug 23 05:14:37 PM UTC 24 Aug 23 05:14:54 PM UTC 24 13975690041 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.441062857 Aug 23 05:14:43 PM UTC 24 Aug 23 05:14:54 PM UTC 24 3180759795 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3111766377 Aug 23 05:14:32 PM UTC 24 Aug 23 05:14:54 PM UTC 24 7649116146 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.1847402084 Aug 23 05:14:48 PM UTC 24 Aug 23 05:14:54 PM UTC 24 6200964139 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2553943302 Aug 23 05:14:50 PM UTC 24 Aug 23 05:14:54 PM UTC 24 3165562792 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.1188893672 Aug 23 05:14:52 PM UTC 24 Aug 23 05:14:55 PM UTC 24 1787778735 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.261557721 Aug 23 05:14:53 PM UTC 24 Aug 23 05:14:55 PM UTC 24 36335183 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2794823643 Aug 23 05:14:49 PM UTC 24 Aug 23 05:14:56 PM UTC 24 6282931825 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.2555742699 Aug 23 05:14:51 PM UTC 24 Aug 23 05:14:56 PM UTC 24 4859304496 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.3545738945 Aug 23 05:14:52 PM UTC 24 Aug 23 05:14:56 PM UTC 24 4054184460 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1084641042 Aug 23 05:14:54 PM UTC 24 Aug 23 05:14:56 PM UTC 24 86009660 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.686430660 Aug 23 05:14:45 PM UTC 24 Aug 23 05:14:57 PM UTC 24 3191153553 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.1191542326 Aug 23 05:14:55 PM UTC 24 Aug 23 05:14:57 PM UTC 24 118811320 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.974850420 Aug 23 05:14:55 PM UTC 24 Aug 23 05:14:57 PM UTC 24 76588032 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.354345144 Aug 23 05:14:55 PM UTC 24 Aug 23 05:14:57 PM UTC 24 79674302 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.4012680669 Aug 23 05:14:56 PM UTC 24 Aug 23 05:14:58 PM UTC 24 115257456 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2571056139 Aug 23 05:14:54 PM UTC 24 Aug 23 05:14:58 PM UTC 24 2457247983 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.694533497 Aug 23 05:14:57 PM UTC 24 Aug 23 05:14:58 PM UTC 24 38545722 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.515459473 Aug 23 05:14:58 PM UTC 24 Aug 23 05:14:59 PM UTC 24 85050782 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3369411688 Aug 23 05:14:58 PM UTC 24 Aug 23 05:14:59 PM UTC 24 93829875 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2680360328 Aug 23 05:14:42 PM UTC 24 Aug 23 05:15:00 PM UTC 24 7035063652 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.3963756051 Aug 23 05:14:58 PM UTC 24 Aug 23 05:15:00 PM UTC 24 2997141589 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.4192933210 Aug 23 05:14:59 PM UTC 24 Aug 23 05:15:00 PM UTC 24 47925414 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.2907756648 Aug 23 05:14:59 PM UTC 24 Aug 23 05:15:00 PM UTC 24 86004865 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.484113392 Aug 23 05:14:56 PM UTC 24 Aug 23 05:15:01 PM UTC 24 3220347442 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.1390915983 Aug 23 05:14:55 PM UTC 24 Aug 23 05:15:01 PM UTC 24 5059277043 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.1842498908 Aug 23 05:14:54 PM UTC 24 Aug 23 05:15:01 PM UTC 24 3529126272 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.2456571598 Aug 23 05:14:58 PM UTC 24 Aug 23 05:15:02 PM UTC 24 765027130 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.4045962290 Aug 23 05:15:00 PM UTC 24 Aug 23 05:15:02 PM UTC 24 99190655 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3992817678 Aug 23 05:14:04 PM UTC 24 Aug 23 05:15:02 PM UTC 24 10797208100 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.3501250653 Aug 23 05:15:00 PM UTC 24 Aug 23 05:15:03 PM UTC 24 650047291 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.3271429971 Aug 23 05:14:11 PM UTC 24 Aug 23 05:15:03 PM UTC 24 13162178983 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3281044110 Aug 23 05:15:01 PM UTC 24 Aug 23 05:15:03 PM UTC 24 53646784 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1486607026 Aug 23 05:15:01 PM UTC 24 Aug 23 05:15:03 PM UTC 24 211463407 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.4156731162 Aug 23 05:13:36 PM UTC 24 Aug 23 05:15:03 PM UTC 24 32998234177 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.1294506708 Aug 23 05:14:59 PM UTC 24 Aug 23 05:15:04 PM UTC 24 4566535253 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3808807477 Aug 23 05:15:02 PM UTC 24 Aug 23 05:15:04 PM UTC 24 246680004 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.1709714042 Aug 23 05:15:02 PM UTC 24 Aug 23 05:15:04 PM UTC 24 155125586 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.3012947054 Aug 23 05:15:01 PM UTC 24 Aug 23 05:15:05 PM UTC 24 3342386562 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.4074057832 Aug 23 05:15:03 PM UTC 24 Aug 23 05:15:05 PM UTC 24 56143554 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.2687422137 Aug 23 05:15:03 PM UTC 24 Aug 23 05:15:05 PM UTC 24 39212713 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.2867249563 Aug 23 05:15:03 PM UTC 24 Aug 23 05:15:05 PM UTC 24 50163290 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2827481929 Aug 23 05:15:01 PM UTC 24 Aug 23 05:15:06 PM UTC 24 1750370437 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.3035890158 Aug 23 05:15:05 PM UTC 24 Aug 23 05:15:06 PM UTC 24 90775259 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.1098850617 Aug 23 05:14:59 PM UTC 24 Aug 23 05:15:06 PM UTC 24 2219218544 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.1101605201 Aug 23 05:15:05 PM UTC 24 Aug 23 05:15:06 PM UTC 24 128695254 ps
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T322 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.3709743209 Aug 23 05:15:10 PM UTC 24 Aug 23 05:15:11 PM UTC 24 51566667 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2958504022 Aug 23 05:15:10 PM UTC 24 Aug 23 05:15:11 PM UTC 24 70033125 ps
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T326 /workspaces/repo/scratch/os_regression_2024_08_22/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.3545906796 Aug 23 05:15:11 PM UTC 24 Aug 23 05:15:13 PM UTC 24 53719405 ps
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