Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	271461	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

589368

1

T1

2

T6

2

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	489432	1			T1	1		T5	1		T39	3
values[0x0]	154469	1			T1	1		T3	2		T6	1
values[0x1]	216928	1			T1	3		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	177200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

683629

1

T1

3

T6

2

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3650	1			T66	21		T189	1		T71	27
valid_sources[0x01]	2991	1			T76	1		T33	1		T64	1
valid_sources[0x02]	3300	1			T10	2		T64	1		T66	25
valid_sources[0x03]	3409	1			T66	14		T71	21		T54	32
valid_sources[0x04]	3283	1			T63	1		T66	13		T67	2
valid_sources[0x05]	3172	1			T64	4		T204	2		T66	38
valid_sources[0x06]	3457	1			T66	7		T71	29		T54	32
valid_sources[0x07]	3338	1			T41	1		T50	1		T60	221
valid_sources[0x08]	2885	1			T60	26		T66	9		T71	23
valid_sources[0x09]	3267	1			T3	1		T66	12		T71	22
valid_sources[0x0a]	3094	1			T66	16		T12	1		T71	27
valid_sources[0x0b]	3056	1			T66	30		T68	11		T71	35
valid_sources[0x0c]	2959	1			T64	4		T66	19		T28	1
valid_sources[0x0d]	2927	1			T60	33		T66	4		T71	33
valid_sources[0x0e]	3773	1			T66	10		T71	27		T54	25
valid_sources[0x0f]	3697	1			T64	1		T66	23		T71	29
valid_sources[0x10]	3462	1			T56	6		T205	1		T66	17
valid_sources[0x11]	3831	1			T66	12		T71	24		T54	35
valid_sources[0x12]	2938	1			T64	1		T66	14		T71	15
valid_sources[0x13]	3306	1			T66	16		T71	26		T54	37
valid_sources[0x14]	2915	1			T66	8		T71	20		T54	50
valid_sources[0x15]	3385	1			T66	14		T71	19		T54	25
valid_sources[0x16]	3356	1			T60	9		T66	18		T12	1
valid_sources[0x17]	3419	1			T60	40		T66	24		T189	1
valid_sources[0x18]	3040	1			T64	1		T66	13		T71	10
valid_sources[0x19]	2862	1			T64	2		T70	1		T66	16
valid_sources[0x1a]	3598	1			T64	1		T59	9		T66	14
valid_sources[0x1b]	3293	1			T63	3		T57	2		T66	20
valid_sources[0x1c]	3277	1			T25	2		T64	1		T66	7
valid_sources[0x1d]	3220	1			T60	19		T66	19		T71	22
valid_sources[0x1e]	3570	1			T40	4		T60	7		T66	8
valid_sources[0x1f]	2801	1			T66	19		T71	34		T54	20
valid_sources[0x20]	3560	1			T66	18		T71	29		T54	13
valid_sources[0x21]	3176	1			T64	1		T66	15		T71	17
valid_sources[0x22]	3242	1			T206	2		T70	2		T66	14
valid_sources[0x23]	3611	1			T66	19		T71	27		T54	40
valid_sources[0x24]	2905	1			T64	1		T66	24		T67	1
valid_sources[0x25]	3724	1			T64	1		T66	12		T71	31
valid_sources[0x26]	3200	1			T66	10		T71	16		T54	38
valid_sources[0x27]	3142	1			T60	9		T66	13		T71	22
valid_sources[0x28]	3207	1			T60	1		T66	14		T71	22
valid_sources[0x29]	3008	1			T66	10		T71	26		T54	17
valid_sources[0x2a]	3524	1			T63	1		T66	18		T71	30
valid_sources[0x2b]	3456	1			T92	1		T66	22		T71	23
valid_sources[0x2c]	3256	1			T64	1		T66	10		T71	18
valid_sources[0x2d]	4382	1			T51	1		T58	2		T9	1
valid_sources[0x2e]	3542	1			T63	1		T101	1		T27	2
valid_sources[0x2f]	3613	1			T66	9		T71	32		T54	22
valid_sources[0x30]	3873	1			T60	71		T72	2		T66	17
valid_sources[0x31]	3263	1			T63	2		T64	1		T60	4
valid_sources[0x32]	3225	1			T51	2		T60	28		T66	23
valid_sources[0x33]	3285	1			T63	1		T41	1		T64	1
valid_sources[0x34]	3449	1			T63	1		T66	15		T207	11
valid_sources[0x35]	3505	1			T66	21		T71	20		T54	27
valid_sources[0x36]	3396	1			T60	85		T66	16		T71	18
valid_sources[0x37]	4628	1			T63	3		T66	18		T67	1
valid_sources[0x38]	3241	1			T66	16		T71	26		T54	27
valid_sources[0x39]	3582	1			T66	22		T71	22		T54	24
valid_sources[0x3a]	3497	1			T66	14		T71	23		T54	17
valid_sources[0x3b]	3677	1			T60	135		T66	17		T71	20
valid_sources[0x3c]	4134	1			T66	14		T71	29		T54	50
valid_sources[0x3d]	3478	1			T42	1		T66	13		T71	19
valid_sources[0x3e]	3411	1			T66	18		T71	31		T54	27
valid_sources[0x3f]	3377	1			T60	6		T66	13		T71	24
valid_sources[0x40]	3363	1			T63	6		T64	2		T66	15
valid_sources[0x41]	3746	1			T24	1		T66	10		T71	28
valid_sources[0x42]	3299	1			T72	1		T66	29		T28	1
valid_sources[0x43]	3136	1			T74	2		T66	12		T71	28
valid_sources[0x44]	3105	1			T60	23		T66	12		T71	24
valid_sources[0x45]	3244	1			T66	6		T71	28		T54	21
valid_sources[0x46]	3322	1			T66	10		T71	19		T54	18
valid_sources[0x47]	2939	1			T63	1		T60	12		T66	17
valid_sources[0x48]	2899	1			T51	2		T66	7		T12	1
valid_sources[0x49]	3803	1			T66	17		T71	26		T54	35
valid_sources[0x4a]	2756	1			T24	1		T66	19		T71	20
valid_sources[0x4b]	3787	1			T66	10		T71	20		T54	25
valid_sources[0x4c]	3457	1			T64	1		T66	11		T28	2
valid_sources[0x4d]	3874	1			T63	4		T66	9		T71	32
valid_sources[0x4e]	4276	1			T63	2		T66	27		T71	27
valid_sources[0x4f]	3255	1			T51	1		T66	12		T71	22
valid_sources[0x50]	3020	1			T64	1		T60	91		T66	14
valid_sources[0x51]	3608	1			T63	1		T93	3		T66	20
valid_sources[0x52]	3112	1			T63	1		T60	26		T66	20
valid_sources[0x53]	3483	1			T66	19		T71	32		T54	58
valid_sources[0x54]	3292	1			T60	178		T66	12		T71	32
valid_sources[0x55]	3110	1			T63	7		T89	1		T66	15
valid_sources[0x56]	3180	1			T41	1		T60	11		T66	16
valid_sources[0x57]	2986	1			T66	11		T11	6		T71	25
valid_sources[0x58]	3355	1			T64	3		T66	25		T71	26
valid_sources[0x59]	3378	1			T60	36		T66	18		T12	1
valid_sources[0x5a]	3129	1			T60	236		T66	10		T71	19
valid_sources[0x5b]	3110	1			T64	2		T60	6		T66	13
valid_sources[0x5c]	2985	1			T53	1		T62	1		T60	143
valid_sources[0x5d]	3104	1			T64	1		T66	14		T71	26
valid_sources[0x5e]	3595	1			T41	1		T64	1		T66	17
valid_sources[0x5f]	3148	1			T60	16		T66	18		T71	36
valid_sources[0x60]	3685	1			T66	8		T71	31		T54	20
valid_sources[0x61]	2973	1			T63	1		T41	1		T102	2
valid_sources[0x62]	3435	1			T63	1		T66	8		T71	29
valid_sources[0x63]	3244	1			T66	29		T71	20		T54	24
valid_sources[0x64]	3494	1			T64	2		T60	22		T66	15
valid_sources[0x65]	3732	1			T60	217		T66	13		T71	25
valid_sources[0x66]	3560	1			T3	1		T63	6		T66	18
valid_sources[0x67]	3300	1			T66	16		T71	34		T54	31
valid_sources[0x68]	3227	1			T63	1		T51	1		T27	1
valid_sources[0x69]	3385	1			T205	1		T66	22		T34	10
valid_sources[0x6a]	3640	1			T64	1		T66	19		T71	25
valid_sources[0x6b]	3305	1			T60	135		T66	16		T71	25
valid_sources[0x6c]	3828	1			T66	14		T71	25		T54	45
valid_sources[0x6d]	3572	1			T64	2		T66	35		T67	1
valid_sources[0x6e]	3563	1			T205	1		T66	14		T67	1
valid_sources[0x6f]	3746	1			T53	1		T66	11		T71	26
valid_sources[0x70]	3743	1			T66	17		T71	28		T54	19
valid_sources[0x71]	2523	1			T58	2		T66	13		T71	24
valid_sources[0x72]	2987	1			T3	1		T66	9		T71	38
valid_sources[0x73]	3226	1			T58	2		T66	20		T71	25
valid_sources[0x74]	3373	1			T66	20		T71	21		T54	45
valid_sources[0x75]	3390	1			T66	21		T71	22		T54	39
valid_sources[0x76]	3281	1			T64	1		T66	12		T67	1
valid_sources[0x77]	3460	1			T66	13		T71	25		T54	30
valid_sources[0x78]	3665	1			T137	2		T60	135		T66	18
valid_sources[0x79]	3505	1			T64	1		T66	22		T71	18
valid_sources[0x7a]	3393	1			T63	2		T66	16		T71	33
valid_sources[0x7b]	3129	1			T60	63		T66	20		T71	33
valid_sources[0x7c]	2927	1			T63	3		T51	2		T66	8
valid_sources[0x7d]	4479	1			T72	1		T66	14		T179	2
valid_sources[0x7e]	2699	1			T41	1		T57	5		T66	12
valid_sources[0x7f]	3036	1			T66	12		T71	25		T54	25
valid_sources[0x80]	3460	1			T64	1		T66	27		T71	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

297017

1

T1

1

T5

1

T39

2

values[0x0]

all_enables

biggest_size

146518

1

T6

1

T5

1

T33

1

values[0x1]

all_enables

biggest_size

145833

1

T1

1

T6

1

T42

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119013

1

T1

9

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35332	1			T60	442		T66	702		T71	842
values[0x0]	44852	1			T1	5		T3	1		T4	1
values[0x1]	47057	1			T1	4		T2	1		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5356	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

121885

1

T1

9

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	352	1			T60	43		T66	10		T71	9
valid_sources[0x01]	534	1			T60	67		T66	5		T71	7
valid_sources[0x02]	409	1			T60	1		T66	10		T71	11
valid_sources[0x03]	468	1			T76	1		T60	1		T66	15
valid_sources[0x04]	511	1			T66	11		T208	1		T71	9
valid_sources[0x05]	370	1			T60	1		T209	1		T66	11
valid_sources[0x06]	751	1			T30	7		T66	8		T71	9
valid_sources[0x07]	358	1			T9	1		T66	12		T71	12
valid_sources[0x08]	703	1			T66	14		T71	13		T107	19
valid_sources[0x09]	567	1			T66	5		T71	10		T54	50
valid_sources[0x0a]	336	1			T66	12		T71	8		T29	1
valid_sources[0x0b]	391	1			T66	14		T210	2		T71	10
valid_sources[0x0c]	610	1			T66	10		T211	1		T71	7
valid_sources[0x0d]	627	1			T53	1		T51	1		T60	4
valid_sources[0x0e]	542	1			T167	3		T66	10		T28	1
valid_sources[0x0f]	350	1			T66	6		T212	1		T71	7
valid_sources[0x10]	859	1			T66	12		T71	13		T54	281
valid_sources[0x11]	421	1			T66	7		T71	14		T107	26
valid_sources[0x12]	420	1			T89	1		T77	1		T66	12
valid_sources[0x13]	623	1			T66	10		T181	1		T213	1
valid_sources[0x14]	487	1			T60	1		T66	7		T214	1
valid_sources[0x15]	621	1			T66	13		T71	10		T54	151
valid_sources[0x16]	870	1			T167	1		T60	304		T9	1
valid_sources[0x17]	399	1			T66	13		T215	1		T71	15
valid_sources[0x18]	408	1			T66	13		T71	10		T54	2
valid_sources[0x19]	401	1			T66	9		T71	13		T54	1
valid_sources[0x1a]	482	1			T66	10		T71	9		T54	2
valid_sources[0x1b]	597	1			T216	1		T209	1		T66	10
valid_sources[0x1c]	376	1			T51	1		T66	9		T217	1
valid_sources[0x1d]	612	1			T59	1		T137	1		T66	12
valid_sources[0x1e]	653	1			T60	20		T66	10		T71	6
valid_sources[0x1f]	493	1			T45	3		T66	9		T34	1
valid_sources[0x20]	404	1			T218	1		T66	6		T212	1
valid_sources[0x21]	431	1			T50	1		T60	2		T209	3
valid_sources[0x22]	392	1			T18	2		T60	1		T66	4
valid_sources[0x23]	551	1			T66	10		T71	9		T54	188
valid_sources[0x24]	395	1			T43	1		T66	11		T71	10
valid_sources[0x25]	744	1			T4	1		T66	15		T212	1
valid_sources[0x26]	377	1			T209	2		T219	1		T66	6
valid_sources[0x27]	370	1			T60	1		T66	8		T71	17
valid_sources[0x28]	397	1			T60	1		T66	9		T71	20
valid_sources[0x29]	522	1			T66	8		T12	1		T71	19
valid_sources[0x2a]	488	1			T66	9		T179	7		T71	14
valid_sources[0x2b]	637	1			T44	1		T66	9		T71	12
valid_sources[0x2c]	586	1			T1	3		T60	1		T66	5
valid_sources[0x2d]	355	1			T46	5		T66	4		T71	12
valid_sources[0x2e]	374	1			T66	10		T71	15		T107	19
valid_sources[0x2f]	557	1			T66	11		T71	12		T220	2
valid_sources[0x30]	461	1			T37	2		T43	1		T66	7
valid_sources[0x31]	547	1			T51	1		T66	11		T71	12
valid_sources[0x32]	497	1			T60	1		T66	9		T71	12
valid_sources[0x33]	886	1			T66	9		T71	8		T107	21
valid_sources[0x34]	409	1			T72	1		T66	15		T71	10
valid_sources[0x35]	721	1			T167	2		T60	3		T66	4
valid_sources[0x36]	374	1			T5	1		T66	10		T217	1
valid_sources[0x37]	674	1			T84	1		T66	12		T71	17
valid_sources[0x38]	389	1			T60	1		T66	7		T214	1
valid_sources[0x39]	906	1			T209	1		T66	7		T71	10
valid_sources[0x3a]	322	1			T117	1		T66	9		T71	8
valid_sources[0x3b]	421	1			T167	2		T19	1		T8	1
valid_sources[0x3c]	519	1			T9	1		T66	11		T71	16
valid_sources[0x3d]	414	1			T48	1		T209	2		T66	13
valid_sources[0x3e]	707	1			T18	2		T66	15		T217	1
valid_sources[0x3f]	457	1			T66	7		T71	7		T54	1
valid_sources[0x40]	628	1			T209	1		T66	12		T221	1
valid_sources[0x41]	431	1			T44	1		T61	1		T122	1
valid_sources[0x42]	435	1			T66	9		T222	1		T213	1
valid_sources[0x43]	483	1			T66	12		T12	1		T71	14
valid_sources[0x44]	393	1			T26	1		T66	5		T71	11
valid_sources[0x45]	619	1			T9	1		T66	7		T186	1
valid_sources[0x46]	385	1			T44	4		T66	10		T223	1
valid_sources[0x47]	454	1			T99	1		T66	10		T67	1
valid_sources[0x48]	503	1			T66	5		T71	7		T107	20
valid_sources[0x49]	364	1			T45	1		T66	9		T71	9
valid_sources[0x4a]	357	1			T9	1		T66	6		T71	16
valid_sources[0x4b]	409	1			T66	10		T212	1		T213	1
valid_sources[0x4c]	343	1			T167	1		T66	6		T71	9
valid_sources[0x4d]	373	1			T75	1		T66	7		T214	1
valid_sources[0x4e]	520	1			T66	15		T71	11		T107	24
valid_sources[0x4f]	518	1			T91	1		T66	6		T11	3
valid_sources[0x50]	398	1			T66	7		T71	12		T54	1
valid_sources[0x51]	356	1			T38	1		T81	1		T66	15
valid_sources[0x52]	533	1			T37	3		T8	1		T224	1
valid_sources[0x53]	397	1			T1	4		T3	1		T40	1
valid_sources[0x54]	527	1			T66	16		T71	13		T107	19
valid_sources[0x55]	994	1			T216	1		T66	9		T68	8
valid_sources[0x56]	479	1			T124	1		T66	6		T12	1
valid_sources[0x57]	453	1			T225	2		T66	12		T212	1
valid_sources[0x58]	401	1			T66	11		T71	17		T107	16
valid_sources[0x59]	559	1			T66	9		T71	23		T54	1
valid_sources[0x5a]	629	1			T66	10		T71	8		T107	24
valid_sources[0x5b]	583	1			T101	1		T58	1		T66	10
valid_sources[0x5c]	454	1			T66	14		T28	1		T71	15
valid_sources[0x5d]	588	1			T44	1		T66	10		T189	6
valid_sources[0x5e]	466	1			T124	1		T66	7		T212	1
valid_sources[0x5f]	410	1			T98	1		T60	1		T66	13
valid_sources[0x60]	871	1			T66	7		T71	13		T54	1
valid_sources[0x61]	668	1			T79	2		T60	116		T66	16
valid_sources[0x62]	640	1			T66	11		T71	9		T54	236
valid_sources[0x63]	407	1			T66	15		T71	18		T54	3
valid_sources[0x64]	429	1			T66	11		T71	10		T29	1
valid_sources[0x65]	409	1			T66	13		T226	2		T214	1
valid_sources[0x66]	643	1			T41	1		T66	7		T210	1
valid_sources[0x67]	495	1			T168	3		T66	7		T217	2
valid_sources[0x68]	347	1			T18	1		T225	1		T66	8
valid_sources[0x69]	904	1			T60	1		T216	1		T66	13
valid_sources[0x6a]	371	1			T60	1		T66	8		T214	1
valid_sources[0x6b]	371	1			T44	1		T66	8		T217	1
valid_sources[0x6c]	430	1			T60	1		T8	1		T209	3
valid_sources[0x6d]	403	1			T66	9		T71	15		T107	20
valid_sources[0x6e]	516	1			T183	1		T66	16		T214	1
valid_sources[0x6f]	432	1			T124	2		T66	13		T12	1
valid_sources[0x70]	522	1			T78	1		T66	4		T71	14
valid_sources[0x71]	396	1			T124	1		T66	9		T71	17
valid_sources[0x72]	395	1			T66	11		T71	11		T54	2
valid_sources[0x73]	610	1			T86	1		T66	4		T71	9
valid_sources[0x74]	399	1			T45	1		T18	1		T73	1
valid_sources[0x75]	359	1			T66	12		T177	7		T71	12
valid_sources[0x76]	598	1			T60	2		T206	1		T66	9
valid_sources[0x77]	564	1			T66	9		T71	8		T227	1
valid_sources[0x78]	388	1			T16	1		T44	1		T66	9
valid_sources[0x79]	398	1			T167	3		T66	9		T214	1
valid_sources[0x7a]	457	1			T60	105		T19	1		T66	6
valid_sources[0x7b]	408	1			T18	1		T60	1		T66	12
valid_sources[0x7c]	428	1			T15	1		T185	5		T66	10
valid_sources[0x7d]	390	1			T66	9		T71	17		T54	1
valid_sources[0x7e]	445	1			T36	1		T66	14		T212	2
valid_sources[0x7f]	520	1			T86	1		T60	18		T66	15
valid_sources[0x80]	408	1			T14	1		T48	1		T66	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31340

1

T60

413

T66

657

T71

796

values[0x0]

all_enables

biggest_size

43865

1

T1

5

T3

1

T4

1

values[0x1]

all_enables

biggest_size

43808

1

T1

4

T2

1

T6

1