SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1163618 | 1 | T1 | 5 | T2 | 1 | T3 | 3 | ||||
auto[1] | 201640 | 1 | T63 | 80 | T64 | 80 | T60 | 3083 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1365080 | 1 | T1 | 5 | T2 | 1 | T3 | 3 | ||||
values[1] | 15 | 1 | T174 | 3 | T171 | 1 | T175 | 1 | ||||
values[2] | 3 | 1 | T193 | 1 | T194 | 1 | T195 | 1 | ||||
values[3] | 85 | 1 | T171 | 8 | T175 | 5 | T193 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1365066 | 1 | T1 | 5 | T2 | 1 | T3 | 3 | ||||
values[1] | 15 | 1 | T174 | 1 | T175 | 2 | T193 | 1 | ||||
values[2] | 5 | 1 | T174 | 1 | T194 | 1 | T196 | 1 | ||||
values[3] | 98 | 1 | T174 | 3 | T171 | 10 | T175 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1364978 | 1 | T1 | 5 | T2 | 1 | T3 | 3 | ||||
auto[TlIntgErrCmd] | 88 | 1 | T174 | 3 | T171 | 4 | T175 | 7 | ||||
auto[TlIntgErrData] | 102 | 1 | T174 | 2 | T171 | 9 | T175 | 8 | ||||
auto[TlIntgErrBoth] | 90 | 1 | T174 | 5 | T171 | 7 | T175 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 323326 | 0 | T1 | 9 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 323143 | 1 | T1 | 9 | T2 | 1 | T3 | 1 | ||||
values[1] | 15 | 1 | T175 | 1 | T193 | 1 | T197 | 2 | ||||
values[2] | 7 | 1 | T171 | 1 | T193 | 1 | T198 | 1 | ||||
values[3] | 104 | 1 | T174 | 5 | T171 | 8 | T175 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 323137 | 1 | T1 | 9 | T2 | 1 | T3 | 1 | ||||
values[1] | 19 | 1 | T171 | 2 | T175 | 1 | T193 | 1 | ||||
values[2] | 5 | 1 | T174 | 1 | T175 | 1 | T195 | 3 | ||||
values[3] | 90 | 1 | T174 | 3 | T171 | 11 | T175 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 323046 | 1 | T1 | 9 | T2 | 1 | T3 | 1 | ||||
auto[TlIntgErrCmd] | 91 | 1 | T174 | 5 | T171 | 4 | T175 | 7 | ||||
auto[TlIntgErrData] | 97 | 1 | T174 | 4 | T171 | 8 | T175 | 7 | ||||
auto[TlIntgErrBoth] | 92 | 1 | T174 | 1 | T171 | 8 | T175 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |