Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
758856 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
3 |
full_word |
606402 |
1 |
|
|
T1 |
2 |
|
T6 |
2 |
|
T5 |
2 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
1364978 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
3 |
auto[TlIntgErrCmd] |
88 |
1 |
|
|
T174 |
3 |
|
T171 |
4 |
|
T175 |
7 |
auto[TlIntgErrData] |
102 |
1 |
|
|
T174 |
2 |
|
T171 |
9 |
|
T175 |
8 |
auto[TlIntgErrBoth] |
90 |
1 |
|
|
T174 |
5 |
|
T171 |
7 |
|
T175 |
5 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
509728 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T39 |
3 |
auto[1] |
855530 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
210800 |
1 |
|
|
T39 |
1 |
|
T10 |
1 |
|
T40 |
8 |
auto[TlIntgErrNone] |
partial |
auto[1] |
547800 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
3 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
298806 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T39 |
2 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
307572 |
1 |
|
|
T1 |
1 |
|
T6 |
2 |
|
T5 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
37 |
1 |
|
|
T171 |
3 |
|
T175 |
2 |
|
T193 |
3 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
44 |
1 |
|
|
T174 |
2 |
|
T171 |
1 |
|
T175 |
4 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
4 |
1 |
|
|
T174 |
1 |
|
T175 |
1 |
|
T199 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
3 |
1 |
|
|
T200 |
1 |
|
T195 |
2 |
|
- |
- |
auto[TlIntgErrData] |
partial |
auto[0] |
43 |
1 |
|
|
T171 |
3 |
|
T175 |
5 |
|
T193 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
50 |
1 |
|
|
T174 |
2 |
|
T171 |
4 |
|
T175 |
3 |
auto[TlIntgErrData] |
full_word |
auto[0] |
2 |
1 |
|
|
T171 |
1 |
|
T196 |
1 |
|
- |
- |
auto[TlIntgErrData] |
full_word |
auto[1] |
7 |
1 |
|
|
T171 |
1 |
|
T195 |
1 |
|
T201 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
33 |
1 |
|
|
T174 |
1 |
|
T171 |
3 |
|
T175 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
49 |
1 |
|
|
T174 |
3 |
|
T171 |
4 |
|
T175 |
3 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
|
T193 |
1 |
|
T202 |
1 |
|
T203 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
5 |
1 |
|
|
T174 |
1 |
|
T193 |
1 |
|
T194 |
1 |