Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	100983691	148796	0	0
late_debug_enable_rd_A	100983691	13942	0	0
late_debug_enable_regwen_rd_A	100983691	13121	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100983691	148796	0	0
T8	283128	0	0	0
T19	164892	0	0	0
T22	0	6063	0	0
T54	0	6759	0	0
T58	200809	0	0	0
T60	102285	2046	0	0
T66	0	3545	0	0
T71	0	3981	0	0
T72	26666	0	0	0
T107	0	7642	0	0
T111	0	5719	0	0
T116	0	12272	0	0
T118	0	9824	0	0
T119	0	9006	0	0
T120	80702	0	0	0
T121	12769	0	0	0
T122	119779	0	0	0
T123	69615	0	0	0
T124	5018	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100983691	13942	0	0
T8	283128	0	0	0
T19	164892	0	0	0
T58	200809	0	0	0
T60	102285	781	0	0
T71	0	1445	0	0
T72	26666	0	0	0
T111	0	2083	0	0
T119	0	3139	0	0
T120	80702	0	0	0
T121	12769	0	0	0
T122	119779	0	0	0
T123	69615	0	0	0
T124	5018	0	0	0
T126	0	5	0	0
T169	0	113	0	0
T170	0	35	0	0
T171	0	25	0	0
T172	0	89	0	0
T173	0	130	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100983691	13121	0	0
T8	283128	0	0	0
T19	164892	0	0	0
T58	200809	0	0	0
T60	102285	658	0	0
T71	0	1307	0	0
T72	26666	0	0	0
T111	0	1974	0	0
T119	0	2919	0	0
T120	80702	0	0	0
T121	12769	0	0	0
T122	119779	0	0	0
T123	69615	0	0	0
T124	5018	0	0	0
T126	0	2	0	0
T128	0	575	0	0
T169	0	85	0	0
T170	0	16	0	0
T171	0	64	0	0
T172	0	86	0	0