Module Definition
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Module : prim_mubi8_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi8_sync_otp_dis_rv_dm_late_debug

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[7].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[4].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[5].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[6].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[7].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_mubi8_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16811100.00

123 end else begin : gen_no_stable_chks 124 1/1 assign mubi = mubi_sync; Tests: T1 T2 T3  125 `ifdef INC_ASSERT 126 mubi8_t mubi_in_sva_q; 127 always_ff @(posedge clk_i) begin 128 1/1 mubi_in_sva_q <= mubi_i; Tests: T1 T2 T3  129 end 130 `ASSERT(OutputDelay_A, 131 rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || 132 $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) 133 `endif 134 end 135 end else begin : gen_no_flops 136 137 //VCS coverage off 138 // pragma coverage off 139 140 // This unused companion logic helps remove lint errors 141 // for modules where clock and reset are used for assertions only 142 // This logic will be removed for synthesis since it is unloaded. 143 mubi8_t unused_logic; 144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 if (!rst_ni) begin 146 unused_logic <= MuBi8False; 147 end else begin 148 unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 assign mubi = MuBi8Width'(mubi_i); 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi8Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi8Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 4/4 assign mubi_o[j] = mubi8_t'(mubi_out); Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

Assert Coverage for Module : prim_mubi8_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 263 263 0 0
OutputsKnown_A 44604544 44530263 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 44604544 44527917 0 789


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 263 263 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T25 1 1 0 0
T35 1 1 0 0
T39 1 1 0 0
T42 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 44604544 44530263 0 0
T1 28956 28644 0 0
T2 14483 14404 0 0
T3 24130 24066 0 0
T4 8355 8274 0 0
T5 32484 32402 0 0
T6 6612 6558 0 0
T25 16723 16661 0 0
T35 33380 33329 0 0
T39 2034 1958 0 0
T42 37296 37235 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 44604544 44527917 0 789
T1 28956 28629 0 3
T2 14483 14401 0 3
T3 24130 24063 0 3
T4 8355 8271 0 3
T5 32484 32399 0 3
T6 6612 6555 0 3
T25 16723 16658 0 3
T35 33380 33326 0 3
T39 2034 1955 0 3
T42 37296 37232 0 3

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