Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
28 logic late_debug_enable;
29 1/1 assign late_debug_enable =
Tests: T1 T2 T3
30 mubi8_test_true_strict(otp_dis_rv_dm_late_debug_i) ||
31 mubi32_test_true_strict(prim_mubi_pkg::mubi32_t'(regs_reg2hw.late_debug_enable));
32
33 // Should debug be enabled? If we're using late_debug_enable, this is governed by
34 // lc_hw_debug_en_i. If not, it comes from lc_dft_en_i.
35 logic debug_enabled;
36 1/1 assign debug_enabled = lc_tx_test_true_strict(late_debug_enable ? lc_hw_debug_en_i : lc_dft_en_i);
Tests: T1 T20 T10
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44603544 |
44529263 |
0 |
0 |
T1 |
28956 |
28644 |
0 |
0 |
T2 |
14483 |
14404 |
0 |
0 |
T3 |
24130 |
24066 |
0 |
0 |
T4 |
8355 |
8274 |
0 |
0 |
T5 |
32484 |
32402 |
0 |
0 |
T6 |
6612 |
6558 |
0 |
0 |
T25 |
16723 |
16661 |
0 |
0 |
T35 |
33380 |
33329 |
0 |
0 |
T39 |
2034 |
1958 |
0 |
0 |
T42 |
37296 |
37235 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44529405 |
44455124 |
0 |
0 |
T1 |
28956 |
28644 |
0 |
0 |
T2 |
14483 |
14404 |
0 |
0 |
T3 |
24130 |
24066 |
0 |
0 |
T4 |
8355 |
8274 |
0 |
0 |
T5 |
32484 |
32402 |
0 |
0 |
T6 |
6612 |
6558 |
0 |
0 |
T25 |
16723 |
16661 |
0 |
0 |
T35 |
33380 |
33329 |
0 |
0 |
T39 |
2034 |
1958 |
0 |
0 |
T42 |
37296 |
37235 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44604544 |
44530263 |
0 |
0 |
T1 |
28956 |
28644 |
0 |
0 |
T2 |
14483 |
14404 |
0 |
0 |
T3 |
24130 |
24066 |
0 |
0 |
T4 |
8355 |
8274 |
0 |
0 |
T5 |
32484 |
32402 |
0 |
0 |
T6 |
6612 |
6558 |
0 |
0 |
T25 |
16723 |
16661 |
0 |
0 |
T35 |
33380 |
33329 |
0 |
0 |
T39 |
2034 |
1958 |
0 |
0 |
T42 |
37296 |
37235 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
44529405 |
44455124 |
0 |
0 |
T1 |
28956 |
28644 |
0 |
0 |
T2 |
14483 |
14404 |
0 |
0 |
T3 |
24130 |
24066 |
0 |
0 |
T4 |
8355 |
8274 |
0 |
0 |
T5 |
32484 |
32402 |
0 |
0 |
T6 |
6612 |
6558 |
0 |
0 |
T25 |
16723 |
16661 |
0 |
0 |
T35 |
33380 |
33329 |
0 |
0 |
T39 |
2034 |
1958 |
0 |
0 |
T42 |
37296 |
37235 |
0 |
0 |