Module Definition
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Module Instance : tb.dut.tl_adapter_host_sba

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.14 100.00 100.00 75.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 100.00 100.00 100.00
u_rsp_chk 93.93 100.00 100.00 75.71 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_host
Line No.TotalCoveredPercent
TOTAL1414100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS13244100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800

93 // bits set. For writes the supplied be_i is used as the mask. 94 1/1 assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i; Tests: T1 T2 T3  95 96 1/1 assign tl_out = '{ Tests: T1 T2 T3  97 a_valid: req_i, 98 a_opcode: (~we_i) ? Get : 99 (&be_i) ? PutFullData : 100 PutPartialData, 101 a_param: 3'h0, 102 a_size: top_pkg::TL_SZW'(WordSize), 103 a_mask: tl_be, 104 a_source: tl_source, 105 a_address: {addr_i[31:WordSize], {WordSize{1'b0}}}, 106 a_data: wdata_i, 107 a_user: '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i}, 108 d_ready: 1'b1 109 }; 110 111 tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen ( 112 .tl_i(tl_out), 113 .tl_o(tl_o) 114 ); 115 116 1/1 assign gnt_o = tl_i.a_ready; Tests: T1 T2 T3  117 118 1/1 assign valid_o = tl_i.d_valid; Tests: T1 T2 T3  119 1/1 assign rdata_o = tl_i.d_data; Tests: T1 T2 T3  120 1/1 assign rdata_intg_o = tl_i.d_user.data_intg; Tests: T1 T2 T3  121 122 logic intg_err; 123 tlul_rsp_intg_chk #( 124 .EnableRspDataIntgCheck(EnableRspDataIntgCheck) 125 ) u_rsp_chk ( 126 .tl_i, 127 .err_o(intg_err) 128 ); 129 130 logic intg_err_q; 131 always_ff @(posedge clk_i or negedge rst_ni) begin 132 1/1 if (!rst_ni) begin Tests: T1 T2 T3  133 1/1 intg_err_q <= '0; Tests: T1 T2 T3  134 1/1 end else if (intg_err) begin Tests: T1 T2 T3  135 1/1 intg_err_q <= 1'b1; Tests: T37 T38 T17  136 end MISSING_ELSE 137 end 138 139 // err_o is transactional. This allows the host to continue 140 // debug without receiving an endless stream of errors. 141 1/1 assign err_o = tl_i.d_error | intg_err; Tests: T1 T2 T3  142 143 // intg_err_o is permanent once detected, and should be used 144 // to trigger alerts 145 1/1 assign intg_err_o = intg_err_q | intg_err; Tests: T1 T2 T3  146 147 // Addresses are assumed to be word-aligned, and the bottom bits are ignored 148 logic unused_addr_bottom_bits; 149 1/1 assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0]; Tests: T1 T2 T3  150 151 // Explicitly ignore unused fields of tl_i 152 logic unused_tl_i_fields; 153 1/1 assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param, Tests: T1 T2 T3  154 tl_i.d_size, tl_i.d_source, tl_i.d_sink, 155 tl_i.d_user}; 156 157 `ifdef INC_ASSERT 158 //VCS coverage off 159 // pragma coverage off 160 localparam int OutstandingReqCntW = 161 (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS); 162 localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1); 163 164 logic [OutstandingReqCntW-1:0] outstanding_reqs_q; 165 logic [OutstandingReqCntW-1:0] outstanding_reqs_d; 166 167 always_comb begin 168 unreachable outstanding_reqs_d = outstanding_reqs_q; 169 170 unreachable if ((req_i && gnt_o) && !valid_o) begin 171 unreachable outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne; 172 unreachable end else if (!(req_i && gnt_o) && valid_o) begin 173 unreachable outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne; 174 end ==> MISSING_ELSE 175 end 176 177 always_ff @(posedge clk_i or negedge rst_ni) begin 178 unreachable if (!rst_ni) begin 179 unreachable outstanding_reqs_q <= '0; 180 end else begin 181 unreachable outstanding_reqs_q <= outstanding_reqs_d;

Cond Coverage for Module : tlul_adapter_host
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT1,T2,T3

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT1,T2,T3

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT14,T15,T16
1CoveredT14,T15,T16

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT52,T14,T16
01CoveredT37,T17,T18
10CoveredT1,T2,T3

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT37,T38,T17
10CoveredT37,T38,T17

Branch Coverage for Module : tlul_adapter_host
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 94 2 2 100.00
IF 132 3 3 100.00


94 assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T14,T15,T16


132 if (!rst_ni) begin -1- 133 intg_err_q <= '0; ==> 134 end else if (intg_err) begin -2- 135 intg_err_q <= 1'b1; ==> 136 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T37,T38,T17
0 0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_host
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 100983691 9728 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 100983691 9728 0 0
T10 11325 0 0 0
T14 61704 69 0 0
T15 39332 3 0 0
T16 159138 9 0 0
T17 0 198 0 0
T37 0 63 0 0
T38 0 9 0 0
T40 3800 0 0 0
T62 0 1 0 0
T63 3678 0 0 0
T76 0 1 0 0
T82 33907 0 0 0
T90 32140 0 0 0
T91 1289 0 0 0
T92 1393 0 0 0
T97 0 50 0 0
T98 0 4 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%