Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T91

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91
1	1	Covered	T91

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	6955252	6953760	0	0
selKnown1	49298539	49297047	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	6955252	6953760	0	0
T1	18577	18573	0	0
T2	1734	1730	0	0
T3	2676	2672	0	0
T4	654	650	0	0
T5	1542	1538	0	0
T6	802	798	0	0
T17	0	14	0	0
T25	1862	1858	0	0
T35	764	760	0	0
T37	0	8	0	0
T38	0	2	0	0
T39	2966	2962	0	0
T42	1092	1088	0	0
T43	0	2	0	0
T47	0	40	0	0
T48	0	1	0	0
T80	0	2	0	0
T82	0	1	0	0
T86	0	4	0	0
T90	0	2	0	0
T91	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	49298539	49297047	0	0
T1	38249	38245	0	0
T2	15351	15347	0	0
T3	25469	25465	0	0
T4	8683	8679	0	0
T5	33256	33252	0	0
T6	7014	7010	0	0
T17	0	14	0	0
T18	0	20	0	0
T25	17655	17651	0	0
T35	33763	33759	0	0
T37	0	8	0	0
T38	0	2	0	0
T39	3518	3514	0	0
T42	37843	37839	0	0
T43	0	2	0	0
T47	0	40	0	0
T48	0	2	0	0
T86	0	8	0	0
T87	0	20	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T91

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91
1	1	Covered	T91

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2261160	2260897	0	0
selKnown1	44604544	44604281	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2261160	2260897	0	0
T1	9283	9282	0	0
T2	866	865	0	0
T3	1337	1336	0	0
T4	326	325	0	0
T5	770	769	0	0
T6	400	399	0	0
T25	930	929	0	0
T35	381	380	0	0
T39	1482	1481	0	0
T42	545	544	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	44604544	44604281	0	0
T1	28956	28955	0	0
T2	14483	14482	0	0
T3	24130	24129	0	0
T4	8355	8354	0	0
T5	32484	32483	0	0
T6	6612	6611	0	0
T25	16723	16722	0	0
T35	33380	33379	0	0
T39	2034	2033	0	0
T42	37296	37295	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T91

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91
1	1	Covered	T91

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	825	562	0	0
selKnown1	782	519	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	825	562	0	0
T1	5	4	0	0
T2	1	0	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T17	0	7	0	0
T25	1	0	0	0
T35	1	0	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	1	0	0	0
T42	1	0	0	0
T43	0	1	0	0
T47	0	20	0	0
T48	0	1	0	0
T80	0	1	0	0
T86	0	4	0	0
T90	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	782	519	0	0
T1	5	4	0	0
T2	1	0	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T17	0	7	0	0
T18	0	10	0	0
T25	1	0	0	0
T35	1	0	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	1	0	0	0
T42	1	0	0	0
T43	0	1	0	0
T47	0	20	0	0
T48	0	1	0	0
T86	0	4	0	0
T87	0	10	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T91

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91
1	1	Covered	T91

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4691508	4691025	0	0
selKnown1	4691507	4691024	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4691508	4691025	0	0
T1	9283	9282	0	0
T2	866	865	0	0
T3	1337	1336	0	0
T4	326	325	0	0
T5	770	769	0	0
T6	400	399	0	0
T25	930	929	0	0
T35	381	380	0	0
T39	1482	1481	0	0
T42	545	544	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	4691507	4691024	0	0
T1	9283	9282	0	0
T2	866	865	0	0
T3	1337	1336	0	0
T4	326	325	0	0
T5	770	769	0	0
T6	400	399	0	0
T25	930	929	0	0
T35	381	380	0	0
T39	1482	1481	0	0
T42	545	544	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T91

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91
1	1	Covered	T91

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T91
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1759	1276	0	0
selKnown1	1706	1223	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1759	1276	0	0
T1	6	5	0	0
T2	1	0	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T17	0	7	0	0
T25	1	0	0	0
T35	1	0	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	1	0	0	0
T42	1	0	0	0
T43	0	1	0	0
T47	0	20	0	0
T80	0	1	0	0
T82	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1706	1223	0	0
T1	5	4	0	0
T2	1	0	0	0
T3	1	0	0	0
T4	1	0	0	0
T5	1	0	0	0
T6	1	0	0	0
T17	0	7	0	0
T18	0	10	0	0
T25	1	0	0	0
T35	1	0	0	0
T37	0	4	0	0
T38	0	1	0	0
T39	1	0	0	0
T42	1	0	0	0
T43	0	1	0	0
T47	0	20	0	0
T48	0	1	0	0
T86	0	4	0	0
T87	0	10	0	0