Line Coverage for Module :
rv_dm_regs_reg_top
| Line No. | Total | Covered | Percent |
TOTAL | | 35 | 35 | 100.00 |
ALWAYS | 67 | 4 | 4 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
ALWAYS | 215 | 4 | 4 | 100.00 |
CONT_ASSIGN | 221 | 1 | 1 | 100.00 |
ALWAYS | 225 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
CONT_ASSIGN | 234 | 1 | 1 | 100.00 |
CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
CONT_ASSIGN | 237 | 1 | 1 | 100.00 |
CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
ALWAYS | 244 | 4 | 4 | 100.00 |
ALWAYS | 252 | 5 | 5 | 100.00 |
CONT_ASSIGN | 277 | 0 | 0 | |
CONT_ASSIGN | 285 | 1 | 1 | 100.00 |
CONT_ASSIGN | 286 | 1 | 1 | 100.00 |
66 always_ff @(posedge clk_i or negedge rst_ni) begin
67 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
68 1/1 err_q <= '0;
Tests: T1 T2 T3
69 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
70 1/1 err_q <= 1'b1;
Tests: T47 T87 T88
71 end
MISSING_ELSE
72 end
73
74 // integrity error output is permanent and should be used for alert generation
75 // register errors are transactional
76 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
77
78 // outgoing integrity generation
79 tlul_pkg::tl_d2h_t tl_o_pre;
80 tlul_rsp_intg_gen #(
81 .EnableRspIntgGen(1),
82 .EnableDataIntgGen(1)
83 ) u_rsp_intg_gen (
84 .tl_i(tl_o_pre),
85 .tl_o(tl_o)
86 );
87
88 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
89 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
90
91 tlul_adapter_reg #(
92 .RegAw(AW),
93 .RegDw(DW),
94 .EnableDataIntgGen(0)
95 ) u_reg_if (
96 .clk_i (clk_i),
97 .rst_ni (rst_ni),
98
99 .tl_i (tl_reg_h2d),
100 .tl_o (tl_reg_d2h),
101
102 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
103 .intg_error_o(),
104
105 .we_o (reg_we),
106 .re_o (reg_re),
107 .addr_o (reg_addr),
108 .wdata_o (reg_wdata),
109 .be_o (reg_be),
110 .busy_i (reg_busy),
111 .rdata_i (reg_rdata),
112 .error_i (reg_error)
113 );
114
115 // cdc oversampling signals
116
117 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
118 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T52 T37 T44
119
120 // Define SW related signals
121 // Format: <reg>_<field>_{wd|we|qs}
122 // or <reg>_{wd|we|qs} if field == 1 or 0
123 logic alert_test_we;
124 logic alert_test_wd;
125 logic late_debug_enable_regwen_we;
126 logic late_debug_enable_regwen_qs;
127 logic late_debug_enable_regwen_wd;
128 logic late_debug_enable_we;
129 logic [31:0] late_debug_enable_qs;
130 logic [31:0] late_debug_enable_wd;
131
132 // Register instances
133 // R[alert_test]: V(True)
134 logic alert_test_qe;
135 logic [0:0] alert_test_flds_we;
136 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T44 T45 T46
137 prim_subreg_ext #(
138 .DW (1)
139 ) u_alert_test (
140 .re (1'b0),
141 .we (alert_test_we),
142 .wd (alert_test_wd),
143 .d ('0),
144 .qre (),
145 .qe (alert_test_flds_we[0]),
146 .q (reg2hw.alert_test.q),
147 .ds (),
148 .qs ()
149 );
150 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T44 T45 T46
151
152
153 // R[late_debug_enable_regwen]: V(False)
154 prim_subreg #(
155 .DW (1),
156 .SwAccess(prim_subreg_pkg::SwAccessW0C),
157 .RESVAL (1'h1),
158 .Mubi (1'b0)
159 ) u_late_debug_enable_regwen (
160 .clk_i (clk_i),
161 .rst_ni (rst_ni),
162
163 // from register interface
164 .we (late_debug_enable_regwen_we),
165 .wd (late_debug_enable_regwen_wd),
166
167 // from internal hardware
168 .de (1'b0),
169 .d ('0),
170
171 // to internal hardware
172 .qe (),
173 .q (),
174 .ds (),
175
176 // to register interface (read)
177 .qs (late_debug_enable_regwen_qs)
178 );
179
180
181 // R[late_debug_enable]: V(False)
182 // Create REGWEN-gated WE signal
183 logic late_debug_enable_gated_we;
184 1/1 assign late_debug_enable_gated_we = late_debug_enable_we & late_debug_enable_regwen_qs;
Tests: T1 T2 T3
185 prim_subreg #(
186 .DW (32),
187 .SwAccess(prim_subreg_pkg::SwAccessRW),
188 .RESVAL (32'h69696969),
189 .Mubi (1'b1)
190 ) u_late_debug_enable (
191 .clk_i (clk_i),
192 .rst_ni (rst_ni),
193
194 // from register interface
195 .we (late_debug_enable_gated_we),
196 .wd (late_debug_enable_wd),
197
198 // from internal hardware
199 .de (1'b0),
200 .d ('0),
201
202 // to internal hardware
203 .qe (),
204 .q (reg2hw.late_debug_enable.q),
205 .ds (),
206
207 // to register interface (read)
208 .qs (late_debug_enable_qs)
209 );
210
211
212
213 logic [2:0] addr_hit;
214 always_comb begin
215 1/1 addr_hit = '0;
Tests: T1 T2 T3
216 1/1 addr_hit[0] = (reg_addr == RV_DM_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
217 1/1 addr_hit[1] = (reg_addr == RV_DM_LATE_DEBUG_ENABLE_REGWEN_OFFSET);
Tests: T1 T2 T3
218 1/1 addr_hit[2] = (reg_addr == RV_DM_LATE_DEBUG_ENABLE_OFFSET);
Tests: T1 T2 T3
219 end
220
221 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
222
223 // Check sub-word write is permitted
224 always_comb begin
225 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
226 ((addr_hit[0] & (|(RV_DM_REGS_PERMIT[0] & ~reg_be))) |
227 (addr_hit[1] & (|(RV_DM_REGS_PERMIT[1] & ~reg_be))) |
228 (addr_hit[2] & (|(RV_DM_REGS_PERMIT[2] & ~reg_be)))));
229 end
230
231 // Generate write-enables
232 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
233
234 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
235 1/1 assign late_debug_enable_regwen_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
236
237 1/1 assign late_debug_enable_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
238 1/1 assign late_debug_enable_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
239
240 1/1 assign late_debug_enable_wd = reg_wdata[31:0];
Tests: T1 T2 T3
241
242 // Assign write-enables to checker logic vector.
243 always_comb begin
244 1/1 reg_we_check = '0;
Tests: T1 T2 T3
245 1/1 reg_we_check[0] = alert_test_we;
Tests: T1 T2 T3
246 1/1 reg_we_check[1] = late_debug_enable_regwen_we;
Tests: T1 T2 T3
247 1/1 reg_we_check[2] = late_debug_enable_gated_we;
Tests: T1 T2 T3
248 end
249
250 // Read data return
251 always_comb begin
252 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
253 1/1 unique case (1'b1)
Tests: T1 T2 T3
254 addr_hit[0]: begin
255 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
256 end
257
258 addr_hit[1]: begin
259 1/1 reg_rdata_next[0] = late_debug_enable_regwen_qs;
Tests: T1 T2 T3
260 end
261
262 addr_hit[2]: begin
263 1/1 reg_rdata_next[31:0] = late_debug_enable_qs;
Tests: T1 T2 T3
264 end
265
266 default: begin
267 reg_rdata_next = '1;
268 end
269 endcase
270 end
271
272 // shadow busy
273 logic shadow_busy;
274 assign shadow_busy = 1'b0;
275
276 // register busy
277 unreachable assign reg_busy = shadow_busy;
278
279 // Unused signal tieoff
280
281 // wdata / byte enable are not always fully used
282 // add a blanket unused statement to handle lint waivers
283 logic unused_wdata;
284 logic unused_be;
285 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
286 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Module :
rv_dm_regs_reg_top
| Total | Covered | Percent |
Conditions | 56 | 56 | 100.00 |
Logical | 56 | 56 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 57
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T60,T66,T71 |
1 | 1 | Covered | T1,T2,T3 |
LINE 69
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T47,T87,T88 |
1 | 0 | Covered | T174,T171,T175 |
LINE 76
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T47,T87,T88 |
0 | 1 | 0 | Covered | T174,T171,T175 |
1 | 0 | 0 | Covered | T47,T87,T88 |
LINE 118
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T174,T171,T175 |
0 | 1 | 0 | Covered | T60,T66,T71 |
1 | 0 | 0 | Covered | T60,T66,T71 |
LINE 184
EXPRESSION (late_debug_enable_we & late_debug_enable_regwen_qs)
----------1--------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T126,T174,T127 |
1 | 1 | Covered | T1,T2,T3 |
LINE 216
EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_ALERT_TEST_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T40,T16 |
LINE 217
EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_REGWEN_OFFSET)
---------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T44,T75 |
LINE 218
EXPRESSION (reg_addr == rv_dm_reg_pkg::RV_DM_LATE_DEBUG_ENABLE_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 221
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 221
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T60,T66,T71 |
LINE 225
EXPRESSION (reg_we & ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))))
---1-- ----------------------------------------------------------------2---------------------------------------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T40 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T60,T66,T71 |
LINE 225
SUB-EXPRESSION ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))))
-------------------1------------------- -------------------2------------------- ---------------------3--------------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T4,T44 |
0 | 1 | 0 | Covered | T44,T47,T64 |
1 | 0 | 0 | Covered | T1,T40,T16 |
LINE 225
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T63 |
1 | 0 | Covered | T1,T16,T63 |
1 | 1 | Covered | T1,T40,T16 |
LINE 225
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T40 |
1 | 0 | Covered | T1,T44,T75 |
1 | 1 | Covered | T44,T47,T64 |
LINE 225
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T40,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T4,T44 |
LINE 232
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T40,T16 |
1 | 1 | 0 | Covered | T60,T66,T71 |
1 | 1 | 1 | Covered | T44,T45,T46 |
LINE 235
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T44,T75 |
1 | 1 | 0 | Covered | T60,T66,T71 |
1 | 1 | 1 | Covered | T125,T126,T174 |
LINE 238
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T44,T45,T46 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T60,T66,T71 |
1 | 1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
rv_dm_regs_reg_top
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
221 |
2 |
2 |
100.00 |
IF |
67 |
3 |
3 |
100.00 |
CASE |
253 |
4 |
4 |
100.00 |
221 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
67 if (!rst_ni) begin
-1-
68 err_q <= '0;
==>
69 end else if (intg_err || reg_we_err) begin
-2-
70 err_q <= 1'b1;
==>
71 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T47,T87,T88 |
0 |
0 |
Covered |
T1,T2,T3 |
253 unique case (1'b1)
-1-
254 addr_hit[0]: begin
255 reg_rdata_next[0] = '0;
==>
256 end
257
258 addr_hit[1]: begin
259 reg_rdata_next[0] = late_debug_enable_regwen_qs;
==>
260 end
261
262 addr_hit[2]: begin
263 reg_rdata_next[31:0] = late_debug_enable_qs;
==>
264 end
265
266 default: begin
267 reg_rdata_next = '1;
==>
Branches:
-1- | Status | Tests |
addr_hit[0] |
Covered |
T1,T2,T3 |
addr_hit[1] |
Covered |
T1,T2,T3 |
addr_hit[2] |
Covered |
T1,T2,T3 |
default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rv_dm_regs_reg_top
Assertion Details
en2addrHit
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100983691 |
13032 |
0 |
0 |
T1 |
28956 |
9 |
0 |
0 |
T2 |
14483 |
1 |
0 |
0 |
T3 |
24130 |
1 |
0 |
0 |
T4 |
8355 |
1 |
0 |
0 |
T5 |
32484 |
1 |
0 |
0 |
T6 |
6612 |
1 |
0 |
0 |
T25 |
16723 |
1 |
0 |
0 |
T35 |
33380 |
1 |
0 |
0 |
T39 |
2034 |
1 |
0 |
0 |
T42 |
37296 |
1 |
0 |
0 |
reAfterRv
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100983691 |
13032 |
0 |
0 |
T1 |
28956 |
9 |
0 |
0 |
T2 |
14483 |
1 |
0 |
0 |
T3 |
24130 |
1 |
0 |
0 |
T4 |
8355 |
1 |
0 |
0 |
T5 |
32484 |
1 |
0 |
0 |
T6 |
6612 |
1 |
0 |
0 |
T25 |
16723 |
1 |
0 |
0 |
T35 |
33380 |
1 |
0 |
0 |
T39 |
2034 |
1 |
0 |
0 |
T42 |
37296 |
1 |
0 |
0 |
rePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100983691 |
6772 |
0 |
0 |
T8 |
283128 |
0 |
0 |
0 |
T19 |
164892 |
0 |
0 |
0 |
T22 |
0 |
83 |
0 |
0 |
T54 |
0 |
91 |
0 |
0 |
T58 |
200809 |
0 |
0 |
0 |
T60 |
102285 |
39 |
0 |
0 |
T66 |
0 |
52 |
0 |
0 |
T71 |
0 |
53 |
0 |
0 |
T72 |
26666 |
0 |
0 |
0 |
T107 |
0 |
112 |
0 |
0 |
T111 |
0 |
60 |
0 |
0 |
T116 |
0 |
157 |
0 |
0 |
T118 |
0 |
141 |
0 |
0 |
T119 |
0 |
123 |
0 |
0 |
T120 |
80702 |
0 |
0 |
0 |
T121 |
12769 |
0 |
0 |
0 |
T122 |
119779 |
0 |
0 |
0 |
T123 |
69615 |
0 |
0 |
0 |
T124 |
5018 |
0 |
0 |
0 |
wePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100983691 |
6260 |
0 |
0 |
T1 |
28956 |
9 |
0 |
0 |
T2 |
14483 |
1 |
0 |
0 |
T3 |
24130 |
1 |
0 |
0 |
T4 |
8355 |
1 |
0 |
0 |
T5 |
32484 |
1 |
0 |
0 |
T6 |
6612 |
1 |
0 |
0 |
T25 |
16723 |
1 |
0 |
0 |
T35 |
33380 |
1 |
0 |
0 |
T39 |
2034 |
1 |
0 |
0 |
T42 |
37296 |
1 |
0 |
0 |