Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 100.00 66.67 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 100.00 66.67 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.83 100.00 87.50 100.00 i_cdc_req


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_rz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 100.00 66.67 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 100.00 66.67 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.78 100.00 93.33 100.00 i_cdc_resp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_rz_hs_protocol.req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN5500
ALWAYS751010100.00
ALWAYS11733100.00
ALWAYS1261111100.00
ALWAYS16933100.00
CONT_ASSIGN33500
ALWAYS33900

54 logic unused_req_chk; 55 unreachable assign unused_req_chk = req_chk_i; 56 57 if (EnRzHs) begin : gen_rz_hs_protocol 58 ////////////////// 59 // RZ protocol // 60 ////////////////// 61 62 // Types 63 typedef enum logic { 64 LoSt, HiSt 65 } rz_fsm_e; 66 67 // Signals 68 rz_fsm_e src_fsm_d, src_fsm_q; 69 rz_fsm_e dst_fsm_d, dst_fsm_q; 70 logic src_ack, dst_ack; 71 logic src_req, dst_req; 72 73 // REQ-side FSM (SRC domain) 74 always_comb begin : src_fsm 75 1/1 src_fsm_d = src_fsm_q; Tests: T1 T2 T3  76 1/1 src_ack_o = 1'b0; Tests: T1 T2 T3  77 1/1 src_req = 1'b0; Tests: T1 T2 T3  78 79 1/1 unique case (src_fsm_q) Tests: T1 T2 T3  80 LoSt: begin 81 // Wait for the ack to go back to zero before starting 82 // a new transaction. 83 1/1 if (!src_ack && src_req_i) begin Tests: T1 T2 T3  84 1/1 src_fsm_d = HiSt; Tests: T1 T2 T3  85 end MISSING_ELSE 86 end 87 HiSt: begin 88 1/1 src_req = 1'b1; Tests: T1 T2 T3  89 // Forward the acknowledgement. 90 1/1 src_ack_o = src_ack; Tests: T1 T2 T3  91 // If request drops out, we go back to LoSt. 92 // If DST side asserts ack, we also go back to LoSt. 93 1/1 if (!src_req_i || src_ack) begin Tests: T1 T2 T3  94 1/1 src_fsm_d = LoSt; Tests: T1 T2 T3  95 end MISSING_ELSE 96 end 97 //VCS coverage off 98 // pragma coverage off 99 default: ; 100 //VCS coverage on 101 // pragma coverage on 102 endcase 103 end 104 105 // Move ACK over to SRC domain. 106 prim_flop_2sync #( 107 .Width(1) 108 ) ack_sync ( 109 .clk_i (clk_src_i), 110 .rst_ni (rst_src_ni), 111 .d_i (dst_ack), 112 .q_o (src_ack) 113 ); 114 115 // Registers 116 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 117 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  118 1/1 src_fsm_q <= LoSt; Tests: T1 T2 T3  119 end else begin 120 1/1 src_fsm_q <= src_fsm_d; Tests: T1 T2 T3  121 end 122 end 123 124 // ACK-side FSM (DST domain) 125 always_comb begin : dst_fsm 126 1/1 dst_fsm_d = dst_fsm_q; Tests: T1 T2 T3  127 1/1 dst_req_o = 1'b0; Tests: T1 T2 T3  128 1/1 dst_ack = 1'b0; Tests: T1 T2 T3  129 130 1/1 unique case (dst_fsm_q) Tests: T1 T2 T3  131 LoSt: begin 132 1/1 if (dst_req) begin Tests: T1 T2 T3  133 // Forward the request. 134 1/1 dst_req_o = 1'b1; Tests: T1 T2 T3  135 // Wait for the request and acknowledge to be asserted 136 // before responding to the SRC side. 137 1/1 if (dst_ack_i) begin Tests: T1 T2 T3  138 1/1 dst_fsm_d = HiSt; Tests: T1 T2 T3  139 end MISSING_ELSE 140 end MISSING_ELSE 141 end 142 HiSt: begin 143 1/1 dst_ack = 1'b1; Tests: T1 T2 T3  144 // Wait for the request to drop back to zero. 145 1/1 if (!dst_req) begin Tests: T1 T2 T3  146 1/1 dst_fsm_d = LoSt; Tests: T1 T2 T3  147 end MISSING_ELSE 148 end 149 //VCS coverage off 150 // pragma coverage off 151 default: ; 152 //VCS coverage on 153 // pragma coverage on 154 endcase 155 end 156 157 // Move REQ over to DST domain. 158 prim_flop_2sync #( 159 .Width(1) 160 ) req_sync ( 161 .clk_i (clk_dst_i), 162 .rst_ni (rst_dst_ni), 163 .d_i (src_req), 164 .q_o (dst_req) 165 ); 166 167 // Registers 168 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 169 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  170 1/1 dst_fsm_q <= LoSt; Tests: T1 T2 T3  171 end else begin 172 1/1 dst_fsm_q <= dst_fsm_d; Tests: T1 T2 T3  173 end 174 end 175 176 end else begin : gen_nrz_hs_protocol 177 ////////////////// 178 // NRZ protocol // 179 ////////////////// 180 181 // Types 182 typedef enum logic { 183 EVEN, ODD 184 } sync_reqack_fsm_e; 185 186 // Signals 187 sync_reqack_fsm_e src_fsm_ns, src_fsm_cs; 188 sync_reqack_fsm_e dst_fsm_ns, dst_fsm_cs; 189 190 logic src_req_d, src_req_q, src_ack; 191 logic dst_ack_d, dst_ack_q, dst_req; 192 logic src_handshake, dst_handshake; 193 194 assign src_handshake = src_req_i & src_ack_o; 195 assign dst_handshake = dst_req_o & dst_ack_i; 196 197 // Move REQ over to DST domain. 198 prim_flop_2sync #( 199 .Width(1) 200 ) req_sync ( 201 .clk_i (clk_dst_i), 202 .rst_ni (rst_dst_ni), 203 .d_i (src_req_q), 204 .q_o (dst_req) 205 ); 206 207 // Move ACK over to SRC domain. 208 prim_flop_2sync #( 209 .Width(1) 210 ) ack_sync ( 211 .clk_i (clk_src_i), 212 .rst_ni (rst_src_ni), 213 .d_i (dst_ack_q), 214 .q_o (src_ack) 215 ); 216 217 // REQ-side FSM (SRC domain) 218 always_comb begin : src_fsm 219 src_fsm_ns = src_fsm_cs; 220 221 // By default, we keep the internal REQ value and don't ACK. 222 src_req_d = src_req_q; 223 src_ack_o = 1'b0; 224 225 unique case (src_fsm_cs) 226 227 EVEN: begin 228 // Simply forward REQ and ACK. 229 src_req_d = src_req_i; 230 src_ack_o = src_ack; 231 232 // The handshake is done for exactly 1 clock cycle. 233 if (src_handshake) begin 234 src_fsm_ns = ODD; 235 end 236 end 237 238 ODD: begin 239 // Internal REQ and ACK have inverted meaning now. If src_req_i is high again, this 240 // signals a new transaction. 241 src_req_d = ~src_req_i; 242 src_ack_o = ~src_ack; 243 244 // The handshake is done for exactly 1 clock cycle. 245 if (src_handshake) begin 246 src_fsm_ns = EVEN; 247 end 248 end 249 250 //VCS coverage off 251 // pragma coverage off 252 253 default: ; 254 255 //VCS coverage on 256 // pragma coverage on 257 258 endcase 259 end 260 261 // ACK-side FSM (DST domain) 262 always_comb begin : dst_fsm 263 dst_fsm_ns = dst_fsm_cs; 264 265 // By default, we don't REQ and keep the internal ACK. 266 dst_req_o = 1'b0; 267 dst_ack_d = dst_ack_q; 268 269 unique case (dst_fsm_cs) 270 271 EVEN: begin 272 // Simply forward REQ and ACK. 273 dst_req_o = dst_req; 274 dst_ack_d = dst_ack_i; 275 276 // The handshake is done for exactly 1 clock cycle. 277 if (dst_handshake) begin 278 dst_fsm_ns = ODD; 279 end 280 end 281 282 ODD: begin 283 // Internal REQ and ACK have inverted meaning now. If dst_req goes low, this signals a new 284 // transaction. 285 dst_req_o = ~dst_req; 286 dst_ack_d = ~dst_ack_i; 287 288 // The handshake is done for exactly 1 clock cycle. 289 if (dst_handshake) begin 290 dst_fsm_ns = EVEN; 291 end 292 end 293 294 //VCS coverage off 295 // pragma coverage off 296 297 default: ; 298 299 //VCS coverage on 300 // pragma coverage on 301 302 endcase 303 end 304 305 // Registers 306 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 307 if (!rst_src_ni) begin 308 src_fsm_cs <= EVEN; 309 src_req_q <= 1'b0; 310 end else begin 311 src_fsm_cs <= src_fsm_ns; 312 src_req_q <= src_req_d; 313 end 314 end 315 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 316 if (!rst_dst_ni) begin 317 dst_fsm_cs <= EVEN; 318 dst_ack_q <= 1'b0; 319 end else begin 320 dst_fsm_cs <= dst_fsm_ns; 321 dst_ack_q <= dst_ack_d; 322 end 323 end 324 end 325 326 //////////////// 327 // Assertions // 328 //////////////// 329 330 `ifdef INC_ASSERT 331 //VCS coverage off 332 // pragma coverage off 333 334 logic effective_rst_n; 335 unreachable assign effective_rst_n = rst_src_ni && rst_dst_ni; 336 337 logic chk_flag; 338 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 339 unreachable if (!effective_rst_n) begin 340 unreachable chk_flag <= '0; 341 unreachable end else if (src_req_i && !chk_flag) begin 342 unreachable chk_flag <= 1'b1; 343 end ==> MISSING_ELSE

Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 13 13 100.00
CASE 79 4 4 100.00
IF 117 2 2 100.00
CASE 130 5 5 100.00
IF 169 2 2 100.00


79 unique case (src_fsm_q) -1- 80 LoSt: begin 81 // Wait for the ack to go back to zero before starting 82 // a new transaction. 83 if (!src_ack && src_req_i) begin -2- 84 src_fsm_d = HiSt; ==> 85 end MISSING_ELSE ==> 86 end 87 HiSt: begin 88 src_req = 1'b1; 89 // Forward the acknowledgement. 90 src_ack_o = src_ack; 91 // If request drops out, we go back to LoSt. 92 // If DST side asserts ack, we also go back to LoSt. 93 if (!src_req_i || src_ack) begin -3- 94 src_fsm_d = LoSt; ==> 95 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
LoSt 1 - Covered T1,T2,T3
LoSt 0 - Covered T1,T2,T3
HiSt - 1 Covered T1,T2,T3
HiSt - 0 Covered T1,T2,T3


117 if (!rst_src_ni) begin -1- 118 src_fsm_q <= LoSt; ==> 119 end else begin 120 src_fsm_q <= src_fsm_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


130 unique case (dst_fsm_q) -1- 131 LoSt: begin 132 if (dst_req) begin -2- 133 // Forward the request. 134 dst_req_o = 1'b1; 135 // Wait for the request and acknowledge to be asserted 136 // before responding to the SRC side. 137 if (dst_ack_i) begin -3- 138 dst_fsm_d = HiSt; ==> 139 end MISSING_ELSE ==> 140 end MISSING_ELSE ==> 141 end 142 HiSt: begin 143 dst_ack = 1'b1; 144 // Wait for the request to drop back to zero. 145 if (!dst_req) begin -4- 146 dst_fsm_d = LoSt; ==> 147 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
LoSt 1 1 - Covered T1,T2,T3
LoSt 1 0 - Covered T1,T2,T3
LoSt 0 - - Covered T1,T2,T3
HiSt - - 1 Covered T1,T2,T3
HiSt - - 0 Covered T1,T2,T3


169 if (!rst_dst_ni) begin -1- 170 dst_fsm_q <= LoSt; ==> 171 end else begin 172 dst_fsm_q <= dst_fsm_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 105675198 79228 0 0
SyncReqAckHoldReq 105675198 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 105675198 79228 0 0
T1 38239 142 0 0
T2 15349 16 0 0
T3 25467 22 0 0
T4 8681 6 0 0
T5 33254 14 0 0
T6 7012 6 0 0
T25 17653 14 0 0
T35 33761 6 0 0
T39 3516 24 0 0
T42 37841 10 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 105675198 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN5500
ALWAYS751010100.00
ALWAYS11733100.00
ALWAYS1261111100.00
ALWAYS16933100.00
CONT_ASSIGN33500
ALWAYS33900

54 logic unused_req_chk; 55 unreachable assign unused_req_chk = req_chk_i; 56 57 if (EnRzHs) begin : gen_rz_hs_protocol 58 ////////////////// 59 // RZ protocol // 60 ////////////////// 61 62 // Types 63 typedef enum logic { 64 LoSt, HiSt 65 } rz_fsm_e; 66 67 // Signals 68 rz_fsm_e src_fsm_d, src_fsm_q; 69 rz_fsm_e dst_fsm_d, dst_fsm_q; 70 logic src_ack, dst_ack; 71 logic src_req, dst_req; 72 73 // REQ-side FSM (SRC domain) 74 always_comb begin : src_fsm 75 1/1 src_fsm_d = src_fsm_q; Tests: T1 T2 T3  76 1/1 src_ack_o = 1'b0; Tests: T1 T2 T3  77 1/1 src_req = 1'b0; Tests: T1 T2 T3  78 79 1/1 unique case (src_fsm_q) Tests: T1 T2 T3  80 LoSt: begin 81 // Wait for the ack to go back to zero before starting 82 // a new transaction. 83 1/1 if (!src_ack && src_req_i) begin Tests: T1 T2 T3  84 1/1 src_fsm_d = HiSt; Tests: T1 T2 T3  85 end MISSING_ELSE 86 end 87 HiSt: begin 88 1/1 src_req = 1'b1; Tests: T1 T2 T3  89 // Forward the acknowledgement. 90 1/1 src_ack_o = src_ack; Tests: T1 T2 T3  91 // If request drops out, we go back to LoSt. 92 // If DST side asserts ack, we also go back to LoSt. 93 1/1 if (!src_req_i || src_ack) begin Tests: T1 T2 T3  94 1/1 src_fsm_d = LoSt; Tests: T1 T2 T3  95 end MISSING_ELSE 96 end 97 //VCS coverage off 98 // pragma coverage off 99 default: ; 100 //VCS coverage on 101 // pragma coverage on 102 endcase 103 end 104 105 // Move ACK over to SRC domain. 106 prim_flop_2sync #( 107 .Width(1) 108 ) ack_sync ( 109 .clk_i (clk_src_i), 110 .rst_ni (rst_src_ni), 111 .d_i (dst_ack), 112 .q_o (src_ack) 113 ); 114 115 // Registers 116 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 117 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  118 1/1 src_fsm_q <= LoSt; Tests: T1 T2 T3  119 end else begin 120 1/1 src_fsm_q <= src_fsm_d; Tests: T1 T2 T3  121 end 122 end 123 124 // ACK-side FSM (DST domain) 125 always_comb begin : dst_fsm 126 1/1 dst_fsm_d = dst_fsm_q; Tests: T1 T2 T3  127 1/1 dst_req_o = 1'b0; Tests: T1 T2 T3  128 1/1 dst_ack = 1'b0; Tests: T1 T2 T3  129 130 1/1 unique case (dst_fsm_q) Tests: T1 T2 T3  131 LoSt: begin 132 1/1 if (dst_req) begin Tests: T1 T2 T3  133 // Forward the request. 134 1/1 dst_req_o = 1'b1; Tests: T1 T2 T3  135 // Wait for the request and acknowledge to be asserted 136 // before responding to the SRC side. 137 1/1 if (dst_ack_i) begin Tests: T1 T2 T3  138 1/1 dst_fsm_d = HiSt; Tests: T1 T2 T3  139 end MISSING_ELSE 140 end MISSING_ELSE 141 end 142 HiSt: begin 143 1/1 dst_ack = 1'b1; Tests: T1 T2 T3  144 // Wait for the request to drop back to zero. 145 1/1 if (!dst_req) begin Tests: T1 T2 T3  146 1/1 dst_fsm_d = LoSt; Tests: T1 T2 T3  147 end MISSING_ELSE 148 end 149 //VCS coverage off 150 // pragma coverage off 151 default: ; 152 //VCS coverage on 153 // pragma coverage on 154 endcase 155 end 156 157 // Move REQ over to DST domain. 158 prim_flop_2sync #( 159 .Width(1) 160 ) req_sync ( 161 .clk_i (clk_dst_i), 162 .rst_ni (rst_dst_ni), 163 .d_i (src_req), 164 .q_o (dst_req) 165 ); 166 167 // Registers 168 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 169 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  170 1/1 dst_fsm_q <= LoSt; Tests: T1 T2 T3  171 end else begin 172 1/1 dst_fsm_q <= dst_fsm_d; Tests: T1 T2 T3  173 end 174 end 175 176 end else begin : gen_nrz_hs_protocol 177 ////////////////// 178 // NRZ protocol // 179 ////////////////// 180 181 // Types 182 typedef enum logic { 183 EVEN, ODD 184 } sync_reqack_fsm_e; 185 186 // Signals 187 sync_reqack_fsm_e src_fsm_ns, src_fsm_cs; 188 sync_reqack_fsm_e dst_fsm_ns, dst_fsm_cs; 189 190 logic src_req_d, src_req_q, src_ack; 191 logic dst_ack_d, dst_ack_q, dst_req; 192 logic src_handshake, dst_handshake; 193 194 assign src_handshake = src_req_i & src_ack_o; 195 assign dst_handshake = dst_req_o & dst_ack_i; 196 197 // Move REQ over to DST domain. 198 prim_flop_2sync #( 199 .Width(1) 200 ) req_sync ( 201 .clk_i (clk_dst_i), 202 .rst_ni (rst_dst_ni), 203 .d_i (src_req_q), 204 .q_o (dst_req) 205 ); 206 207 // Move ACK over to SRC domain. 208 prim_flop_2sync #( 209 .Width(1) 210 ) ack_sync ( 211 .clk_i (clk_src_i), 212 .rst_ni (rst_src_ni), 213 .d_i (dst_ack_q), 214 .q_o (src_ack) 215 ); 216 217 // REQ-side FSM (SRC domain) 218 always_comb begin : src_fsm 219 src_fsm_ns = src_fsm_cs; 220 221 // By default, we keep the internal REQ value and don't ACK. 222 src_req_d = src_req_q; 223 src_ack_o = 1'b0; 224 225 unique case (src_fsm_cs) 226 227 EVEN: begin 228 // Simply forward REQ and ACK. 229 src_req_d = src_req_i; 230 src_ack_o = src_ack; 231 232 // The handshake is done for exactly 1 clock cycle. 233 if (src_handshake) begin 234 src_fsm_ns = ODD; 235 end 236 end 237 238 ODD: begin 239 // Internal REQ and ACK have inverted meaning now. If src_req_i is high again, this 240 // signals a new transaction. 241 src_req_d = ~src_req_i; 242 src_ack_o = ~src_ack; 243 244 // The handshake is done for exactly 1 clock cycle. 245 if (src_handshake) begin 246 src_fsm_ns = EVEN; 247 end 248 end 249 250 //VCS coverage off 251 // pragma coverage off 252 253 default: ; 254 255 //VCS coverage on 256 // pragma coverage on 257 258 endcase 259 end 260 261 // ACK-side FSM (DST domain) 262 always_comb begin : dst_fsm 263 dst_fsm_ns = dst_fsm_cs; 264 265 // By default, we don't REQ and keep the internal ACK. 266 dst_req_o = 1'b0; 267 dst_ack_d = dst_ack_q; 268 269 unique case (dst_fsm_cs) 270 271 EVEN: begin 272 // Simply forward REQ and ACK. 273 dst_req_o = dst_req; 274 dst_ack_d = dst_ack_i; 275 276 // The handshake is done for exactly 1 clock cycle. 277 if (dst_handshake) begin 278 dst_fsm_ns = ODD; 279 end 280 end 281 282 ODD: begin 283 // Internal REQ and ACK have inverted meaning now. If dst_req goes low, this signals a new 284 // transaction. 285 dst_req_o = ~dst_req; 286 dst_ack_d = ~dst_ack_i; 287 288 // The handshake is done for exactly 1 clock cycle. 289 if (dst_handshake) begin 290 dst_fsm_ns = EVEN; 291 end 292 end 293 294 //VCS coverage off 295 // pragma coverage off 296 297 default: ; 298 299 //VCS coverage on 300 // pragma coverage on 301 302 endcase 303 end 304 305 // Registers 306 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 307 if (!rst_src_ni) begin 308 src_fsm_cs <= EVEN; 309 src_req_q <= 1'b0; 310 end else begin 311 src_fsm_cs <= src_fsm_ns; 312 src_req_q <= src_req_d; 313 end 314 end 315 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 316 if (!rst_dst_ni) begin 317 dst_fsm_cs <= EVEN; 318 dst_ack_q <= 1'b0; 319 end else begin 320 dst_fsm_cs <= dst_fsm_ns; 321 dst_ack_q <= dst_ack_d; 322 end 323 end 324 end 325 326 //////////////// 327 // Assertions // 328 //////////////// 329 330 `ifdef INC_ASSERT 331 //VCS coverage off 332 // pragma coverage off 333 334 logic effective_rst_n; 335 unreachable assign effective_rst_n = rst_src_ni && rst_dst_ni; 336 337 logic chk_flag; 338 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 339 unreachable if (!effective_rst_n) begin 340 unreachable chk_flag <= '0; 341 unreachable end else if (src_req_i && !chk_flag) begin 342 unreachable chk_flag <= 1'b1; 343 end ==> MISSING_ELSE

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
Line No.TotalCoveredPercent
Branches 13 13 100.00
CASE 79 4 4 100.00
IF 117 2 2 100.00
CASE 130 5 5 100.00
IF 169 2 2 100.00


79 unique case (src_fsm_q) -1- 80 LoSt: begin 81 // Wait for the ack to go back to zero before starting 82 // a new transaction. 83 if (!src_ack && src_req_i) begin -2- 84 src_fsm_d = HiSt; ==> 85 end MISSING_ELSE ==> 86 end 87 HiSt: begin 88 src_req = 1'b1; 89 // Forward the acknowledgement. 90 src_ack_o = src_ack; 91 // If request drops out, we go back to LoSt. 92 // If DST side asserts ack, we also go back to LoSt. 93 if (!src_req_i || src_ack) begin -3- 94 src_fsm_d = LoSt; ==> 95 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
LoSt 1 - Covered T1,T2,T3
LoSt 0 - Covered T1,T2,T3
HiSt - 1 Covered T1,T2,T3
HiSt - 0 Covered T1,T2,T3


117 if (!rst_src_ni) begin -1- 118 src_fsm_q <= LoSt; ==> 119 end else begin 120 src_fsm_q <= src_fsm_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


130 unique case (dst_fsm_q) -1- 131 LoSt: begin 132 if (dst_req) begin -2- 133 // Forward the request. 134 dst_req_o = 1'b1; 135 // Wait for the request and acknowledge to be asserted 136 // before responding to the SRC side. 137 if (dst_ack_i) begin -3- 138 dst_fsm_d = HiSt; ==> 139 end MISSING_ELSE ==> 140 end MISSING_ELSE ==> 141 end 142 HiSt: begin 143 dst_ack = 1'b1; 144 // Wait for the request to drop back to zero. 145 if (!dst_req) begin -4- 146 dst_fsm_d = LoSt; ==> 147 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTests
LoSt 1 1 - Covered T1,T2,T3
LoSt 1 0 - Covered T1,T2,T3
LoSt 0 - - Covered T1,T2,T3
HiSt - - 1 Covered T1,T2,T3
HiSt - - 0 Covered T1,T2,T3


169 if (!rst_dst_ni) begin -1- 170 dst_fsm_q <= LoSt; ==> 171 end else begin 172 dst_fsm_q <= dst_fsm_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 100983691 39617 0 0
SyncReqAckHoldReq 4691507 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 100983691 39617 0 0
T1 28956 71 0 0
T2 14483 8 0 0
T3 24130 11 0 0
T4 8355 3 0 0
T5 32484 7 0 0
T6 6612 3 0 0
T25 16723 7 0 0
T35 33380 3 0 0
T39 2034 12 0 0
T42 37296 5 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 4691507 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN5500
ALWAYS751010100.00
ALWAYS11733100.00
ALWAYS1261111100.00
ALWAYS16933100.00
CONT_ASSIGN33500
ALWAYS33900

54 logic unused_req_chk; 55 unreachable assign unused_req_chk = req_chk_i; 56 57 if (EnRzHs) begin : gen_rz_hs_protocol 58 ////////////////// 59 // RZ protocol // 60 ////////////////// 61 62 // Types 63 typedef enum logic { 64 LoSt, HiSt 65 } rz_fsm_e; 66 67 // Signals 68 rz_fsm_e src_fsm_d, src_fsm_q; 69 rz_fsm_e dst_fsm_d, dst_fsm_q; 70 logic src_ack, dst_ack; 71 logic src_req, dst_req; 72 73 // REQ-side FSM (SRC domain) 74 always_comb begin : src_fsm 75 1/1 src_fsm_d = src_fsm_q; Tests: T1 T2 T3  76 1/1 src_ack_o = 1'b0; Tests: T1 T2 T3  77 1/1 src_req = 1'b0; Tests: T1 T2 T3  78 79 1/1 unique case (src_fsm_q) Tests: T1 T2 T3  80 LoSt: begin 81 // Wait for the ack to go back to zero before starting 82 // a new transaction. 83 1/1 if (!src_ack && src_req_i) begin Tests: T1 T2 T3  84 1/1 src_fsm_d = HiSt; Tests: T1 T2 T3  85 end MISSING_ELSE 86 end 87 HiSt: begin 88 1/1 src_req = 1'b1; Tests: T1 T2 T3  89 // Forward the acknowledgement. 90 1/1 src_ack_o = src_ack; Tests: T1 T2 T3  91 // If request drops out, we go back to LoSt. 92 // If DST side asserts ack, we also go back to LoSt. 93 1/1 if (!src_req_i || src_ack) begin Tests: T1 T2 T3  94 1/1 src_fsm_d = LoSt; Tests: T1 T2 T3  95 end MISSING_ELSE 96 end 97 //VCS coverage off 98 // pragma coverage off 99 default: ; 100 //VCS coverage on 101 // pragma coverage on 102 endcase 103 end 104 105 // Move ACK over to SRC domain. 106 prim_flop_2sync #( 107 .Width(1) 108 ) ack_sync ( 109 .clk_i (clk_src_i), 110 .rst_ni (rst_src_ni), 111 .d_i (dst_ack), 112 .q_o (src_ack) 113 ); 114 115 // Registers 116 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 117 1/1 if (!rst_src_ni) begin Tests: T1 T2 T3  118 1/1 src_fsm_q <= LoSt; Tests: T1 T2 T3  119 end else begin 120 1/1 src_fsm_q <= src_fsm_d; Tests: T1 T2 T3  121 end 122 end 123 124 // ACK-side FSM (DST domain) 125 always_comb begin : dst_fsm 126 1/1 dst_fsm_d = dst_fsm_q; Tests: T1 T2 T3  127 1/1 dst_req_o = 1'b0; Tests: T1 T2 T3  128 1/1 dst_ack = 1'b0; Tests: T1 T2 T3  129 130 1/1 unique case (dst_fsm_q) Tests: T1 T2 T3  131 LoSt: begin 132 1/1 if (dst_req) begin Tests: T1 T2 T3  133 // Forward the request. 134 1/1 dst_req_o = 1'b1; Tests: T1 T2 T3  135 // Wait for the request and acknowledge to be asserted 136 // before responding to the SRC side. 137 1/1 if (dst_ack_i) begin Tests: T1 T2 T3  138 1/1 dst_fsm_d = HiSt; Tests: T1 T2 T3  139 end ==> MISSING_ELSE 140 end MISSING_ELSE 141 end 142 HiSt: begin 143 1/1 dst_ack = 1'b1; Tests: T1 T2 T3  144 // Wait for the request to drop back to zero. 145 1/1 if (!dst_req) begin Tests: T1 T2 T3  146 1/1 dst_fsm_d = LoSt; Tests: T1 T2 T3  147 end MISSING_ELSE 148 end 149 //VCS coverage off 150 // pragma coverage off 151 default: ; 152 //VCS coverage on 153 // pragma coverage on 154 endcase 155 end 156 157 // Move REQ over to DST domain. 158 prim_flop_2sync #( 159 .Width(1) 160 ) req_sync ( 161 .clk_i (clk_dst_i), 162 .rst_ni (rst_dst_ni), 163 .d_i (src_req), 164 .q_o (dst_req) 165 ); 166 167 // Registers 168 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 169 1/1 if (!rst_dst_ni) begin Tests: T1 T2 T3  170 1/1 dst_fsm_q <= LoSt; Tests: T1 T2 T3  171 end else begin 172 1/1 dst_fsm_q <= dst_fsm_d; Tests: T1 T2 T3  173 end 174 end 175 176 end else begin : gen_nrz_hs_protocol 177 ////////////////// 178 // NRZ protocol // 179 ////////////////// 180 181 // Types 182 typedef enum logic { 183 EVEN, ODD 184 } sync_reqack_fsm_e; 185 186 // Signals 187 sync_reqack_fsm_e src_fsm_ns, src_fsm_cs; 188 sync_reqack_fsm_e dst_fsm_ns, dst_fsm_cs; 189 190 logic src_req_d, src_req_q, src_ack; 191 logic dst_ack_d, dst_ack_q, dst_req; 192 logic src_handshake, dst_handshake; 193 194 assign src_handshake = src_req_i & src_ack_o; 195 assign dst_handshake = dst_req_o & dst_ack_i; 196 197 // Move REQ over to DST domain. 198 prim_flop_2sync #( 199 .Width(1) 200 ) req_sync ( 201 .clk_i (clk_dst_i), 202 .rst_ni (rst_dst_ni), 203 .d_i (src_req_q), 204 .q_o (dst_req) 205 ); 206 207 // Move ACK over to SRC domain. 208 prim_flop_2sync #( 209 .Width(1) 210 ) ack_sync ( 211 .clk_i (clk_src_i), 212 .rst_ni (rst_src_ni), 213 .d_i (dst_ack_q), 214 .q_o (src_ack) 215 ); 216 217 // REQ-side FSM (SRC domain) 218 always_comb begin : src_fsm 219 src_fsm_ns = src_fsm_cs; 220 221 // By default, we keep the internal REQ value and don't ACK. 222 src_req_d = src_req_q; 223 src_ack_o = 1'b0; 224 225 unique case (src_fsm_cs) 226 227 EVEN: begin 228 // Simply forward REQ and ACK. 229 src_req_d = src_req_i; 230 src_ack_o = src_ack; 231 232 // The handshake is done for exactly 1 clock cycle. 233 if (src_handshake) begin 234 src_fsm_ns = ODD; 235 end 236 end 237 238 ODD: begin 239 // Internal REQ and ACK have inverted meaning now. If src_req_i is high again, this 240 // signals a new transaction. 241 src_req_d = ~src_req_i; 242 src_ack_o = ~src_ack; 243 244 // The handshake is done for exactly 1 clock cycle. 245 if (src_handshake) begin 246 src_fsm_ns = EVEN; 247 end 248 end 249 250 //VCS coverage off 251 // pragma coverage off 252 253 default: ; 254 255 //VCS coverage on 256 // pragma coverage on 257 258 endcase 259 end 260 261 // ACK-side FSM (DST domain) 262 always_comb begin : dst_fsm 263 dst_fsm_ns = dst_fsm_cs; 264 265 // By default, we don't REQ and keep the internal ACK. 266 dst_req_o = 1'b0; 267 dst_ack_d = dst_ack_q; 268 269 unique case (dst_fsm_cs) 270 271 EVEN: begin 272 // Simply forward REQ and ACK. 273 dst_req_o = dst_req; 274 dst_ack_d = dst_ack_i; 275 276 // The handshake is done for exactly 1 clock cycle. 277 if (dst_handshake) begin 278 dst_fsm_ns = ODD; 279 end 280 end 281 282 ODD: begin 283 // Internal REQ and ACK have inverted meaning now. If dst_req goes low, this signals a new 284 // transaction. 285 dst_req_o = ~dst_req; 286 dst_ack_d = ~dst_ack_i; 287 288 // The handshake is done for exactly 1 clock cycle. 289 if (dst_handshake) begin 290 dst_fsm_ns = EVEN; 291 end 292 end 293 294 //VCS coverage off 295 // pragma coverage off 296 297 default: ; 298 299 //VCS coverage on 300 // pragma coverage on 301 302 endcase 303 end 304 305 // Registers 306 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin 307 if (!rst_src_ni) begin 308 src_fsm_cs <= EVEN; 309 src_req_q <= 1'b0; 310 end else begin 311 src_fsm_cs <= src_fsm_ns; 312 src_req_q <= src_req_d; 313 end 314 end 315 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin 316 if (!rst_dst_ni) begin 317 dst_fsm_cs <= EVEN; 318 dst_ack_q <= 1'b0; 319 end else begin 320 dst_fsm_cs <= dst_fsm_ns; 321 dst_ack_q <= dst_ack_d; 322 end 323 end 324 end 325 326 //////////////// 327 // Assertions // 328 //////////////// 329 330 `ifdef INC_ASSERT 331 //VCS coverage off 332 // pragma coverage off 333 334 logic effective_rst_n; 335 unreachable assign effective_rst_n = rst_src_ni && rst_dst_ni; 336 337 logic chk_flag; 338 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin 339 unreachable if (!effective_rst_n) begin 340 unreachable chk_flag <= '0; 341 unreachable end else if (src_req_i && !chk_flag) begin 342 unreachable chk_flag <= 1'b1; 343 end ==> MISSING_ELSE

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       83
 EXPRESSION (((!gen_rz_hs_protocol.src_ack)) && src_req_i)
             ---------------1---------------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       93
 EXPRESSION (((!src_req_i)) || gen_rz_hs_protocol.src_ack)
             -------1------    -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 79 4 4 100.00
IF 117 2 2 100.00
CASE 130 4 4 100.00
IF 169 2 2 100.00


79 unique case (src_fsm_q) -1- 80 LoSt: begin 81 // Wait for the ack to go back to zero before starting 82 // a new transaction. 83 if (!src_ack && src_req_i) begin -2- 84 src_fsm_d = HiSt; ==> 85 end MISSING_ELSE ==> 86 end 87 HiSt: begin 88 src_req = 1'b1; 89 // Forward the acknowledgement. 90 src_ack_o = src_ack; 91 // If request drops out, we go back to LoSt. 92 // If DST side asserts ack, we also go back to LoSt. 93 if (!src_req_i || src_ack) begin -3- 94 src_fsm_d = LoSt; ==> 95 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
LoSt 1 - Covered T1,T2,T3
LoSt 0 - Covered T1,T2,T3
HiSt - 1 Covered T1,T2,T3
HiSt - 0 Covered T1,T2,T3


117 if (!rst_src_ni) begin -1- 118 src_fsm_q <= LoSt; ==> 119 end else begin 120 src_fsm_q <= src_fsm_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


130 unique case (dst_fsm_q) -1- 131 LoSt: begin 132 if (dst_req) begin -2- 133 // Forward the request. 134 dst_req_o = 1'b1; 135 // Wait for the request and acknowledge to be asserted 136 // before responding to the SRC side. 137 if (dst_ack_i) begin -3- 138 dst_fsm_d = HiSt; ==> 139 end MISSING_ELSE ==> (Excluded) Exclude Annotation: VC_COV_UNR 140 end MISSING_ELSE ==> 141 end 142 HiSt: begin 143 dst_ack = 1'b1; 144 // Wait for the request to drop back to zero. 145 if (!dst_req) begin -4- 146 dst_fsm_d = LoSt; ==> 147 end MISSING_ELSE ==>

Branches:
-1--2--3--4-StatusTestsExclude Annotation
LoSt 1 1 - Covered T1,T2,T3
LoSt 1 0 - Excluded VC_COV_UNR
LoSt 0 - - Covered T1,T2,T3
HiSt - - 1 Covered T1,T2,T3
HiSt - - 0 Covered T1,T2,T3


169 if (!rst_dst_ni) begin -1- 170 dst_fsm_q <= LoSt; ==> 171 end else begin 172 dst_fsm_q <= dst_fsm_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 4691507 39611 0 0
SyncReqAckHoldReq 100983691 0 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 4691507 39611 0 0
T1 9283 71 0 0
T2 866 8 0 0
T3 1337 11 0 0
T4 326 3 0 0
T5 770 7 0 0
T6 400 3 0 0
T25 930 7 0 0
T35 381 3 0 0
T39 1482 12 0 0
T42 545 5 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 100983691 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%