Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	293110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

639717

1

T3

1

T6

2

T14

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	556186	1			T26	1		T14	1		T47	10
values[0x0]	161704	1			T2	1		T3	1		T13	1
values[0x1]	214937	1			T2	1		T12	3		T26	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197625	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

735202

1

T3

1

T12

1

T6

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3371	1			T63	14		T9	9		T72	63
valid_sources[0x01]	3386	1			T141	1		T63	8		T9	21
valid_sources[0x02]	3565	1			T67	1		T70	7		T63	5
valid_sources[0x03]	3548	1			T44	2		T63	6		T30	1
valid_sources[0x04]	3504	1			T63	12		T9	11		T72	9
valid_sources[0x05]	3785	1			T63	5		T9	3		T72	17
valid_sources[0x06]	3237	1			T67	1		T63	4		T61	2
valid_sources[0x07]	3704	1			T63	8		T9	2		T36	50
valid_sources[0x08]	3014	1			T63	9		T9	6		T31	1
valid_sources[0x09]	3761	1			T226	1		T63	3		T9	8
valid_sources[0x0a]	3161	1			T63	17		T9	21		T72	2
valid_sources[0x0b]	3684	1			T63	7		T9	12		T36	41
valid_sources[0x0c]	3669	1			T63	16		T9	17		T36	36
valid_sources[0x0d]	4302	1			T117	1		T140	1		T63	7
valid_sources[0x0e]	3665	1			T59	3		T63	21		T9	3
valid_sources[0x0f]	5244	1			T57	2		T63	10		T9	8
valid_sources[0x10]	3876	1			T63	8		T60	2		T9	13
valid_sources[0x11]	4119	1			T63	13		T61	1		T9	9
valid_sources[0x12]	3221	1			T67	2		T227	1		T196	1
valid_sources[0x13]	3482	1			T63	9		T9	12		T36	30
valid_sources[0x14]	3814	1			T63	17		T9	2		T72	4
valid_sources[0x15]	3848	1			T63	5		T9	8		T72	11
valid_sources[0x16]	3769	1			T63	11		T9	17		T72	5
valid_sources[0x17]	3760	1			T63	17		T128	1		T9	21
valid_sources[0x18]	3504	1			T63	6		T9	25		T72	1
valid_sources[0x19]	3758	1			T47	2		T63	8		T9	30
valid_sources[0x1a]	3346	1			T47	1		T46	1		T63	15
valid_sources[0x1b]	3742	1			T67	1		T63	5		T9	26
valid_sources[0x1c]	3853	1			T57	2		T63	10		T9	3
valid_sources[0x1d]	4023	1			T63	12		T61	1		T25	1
valid_sources[0x1e]	3377	1			T12	1		T63	2		T9	13
valid_sources[0x1f]	3105	1			T47	1		T67	1		T63	12
valid_sources[0x20]	3721	1			T47	1		T63	14		T9	9
valid_sources[0x21]	3515	1			T67	2		T63	15		T9	5
valid_sources[0x22]	3210	1			T59	3		T63	8		T60	1
valid_sources[0x23]	3401	1			T67	1		T63	8		T9	13
valid_sources[0x24]	3634	1			T63	13		T9	5		T72	16
valid_sources[0x25]	14535	1			T63	11		T9	12		T36	29
valid_sources[0x26]	3576	1			T63	16		T9	17		T72	22
valid_sources[0x27]	4317	1			T63	10		T9	1		T72	12
valid_sources[0x28]	3941	1			T71	1		T63	9		T25	1
valid_sources[0x29]	3535	1			T67	1		T87	1		T63	6
valid_sources[0x2a]	3344	1			T63	15		T9	6		T72	23
valid_sources[0x2b]	3626	1			T63	19		T9	7		T72	6
valid_sources[0x2c]	4384	1			T67	1		T63	10		T9	6
valid_sources[0x2d]	3715	1			T45	2		T66	80		T63	15
valid_sources[0x2e]	3342	1			T12	1		T63	9		T9	7
valid_sources[0x2f]	3595	1			T67	1		T63	11		T9	8
valid_sources[0x30]	3357	1			T14	2		T67	1		T63	5
valid_sources[0x31]	3273	1			T228	2		T63	10		T125	1
valid_sources[0x32]	3868	1			T63	8		T9	10		T72	24
valid_sources[0x33]	4279	1			T63	3		T9	3		T36	35
valid_sources[0x34]	3386	1			T63	8		T9	13		T72	14
valid_sources[0x35]	3909	1			T34	3		T67	1		T71	1
valid_sources[0x36]	3179	1			T63	13		T9	7		T72	190
valid_sources[0x37]	3293	1			T67	1		T32	3		T63	12
valid_sources[0x38]	3438	1			T63	12		T9	17		T72	18
valid_sources[0x39]	3748	1			T63	14		T9	26		T72	9
valid_sources[0x3a]	3992	1			T67	1		T63	10		T9	12
valid_sources[0x3b]	3643	1			T63	23		T9	17		T36	28
valid_sources[0x3c]	3526	1			T63	8		T9	15		T72	13
valid_sources[0x3d]	3229	1			T32	1		T63	19		T9	3
valid_sources[0x3e]	3112	1			T63	27		T9	3		T72	2
valid_sources[0x3f]	3550	1			T32	1		T63	12		T9	10
valid_sources[0x40]	3230	1			T63	10		T9	22		T68	1
valid_sources[0x41]	3254	1			T63	8		T35	1		T9	11
valid_sources[0x42]	3987	1			T67	1		T63	9		T9	13
valid_sources[0x43]	3448	1			T63	5		T9	20		T72	8
valid_sources[0x44]	3623	1			T48	9		T63	8		T9	31
valid_sources[0x45]	3797	1			T63	10		T9	8		T72	6
valid_sources[0x46]	3803	1			T63	7		T60	1		T61	1
valid_sources[0x47]	3375	1			T67	1		T57	1		T63	7
valid_sources[0x48]	3946	1			T63	7		T60	1		T30	2
valid_sources[0x49]	3971	1			T67	1		T63	11		T9	21
valid_sources[0x4a]	3421	1			T62	3		T140	1		T63	11
valid_sources[0x4b]	3301	1			T67	1		T63	15		T9	26
valid_sources[0x4c]	3582	1			T63	19		T9	7		T36	30
valid_sources[0x4d]	3808	1			T42	1		T63	9		T9	25
valid_sources[0x4e]	3735	1			T63	11		T9	9		T36	28
valid_sources[0x4f]	3332	1			T67	1		T63	10		T9	4
valid_sources[0x50]	3565	1			T228	1		T63	10		T9	12
valid_sources[0x51]	3794	1			T63	17		T9	16		T36	43
valid_sources[0x52]	3903	1			T63	12		T9	15		T72	41
valid_sources[0x53]	3651	1			T63	9		T128	2		T9	14
valid_sources[0x54]	3429	1			T67	1		T63	5		T9	27
valid_sources[0x55]	3038	1			T32	1		T63	9		T9	8
valid_sources[0x56]	3378	1			T67	1		T63	17		T9	7
valid_sources[0x57]	3202	1			T63	11		T61	4		T9	8
valid_sources[0x58]	3552	1			T63	4		T9	18		T33	1
valid_sources[0x59]	3420	1			T87	1		T63	8		T60	1
valid_sources[0x5a]	3244	1			T63	17		T9	6		T72	37
valid_sources[0x5b]	3564	1			T63	13		T9	8		T201	3
valid_sources[0x5c]	3725	1			T63	9		T9	8		T33	2
valid_sources[0x5d]	3903	1			T67	1		T63	10		T9	2
valid_sources[0x5e]	3158	1			T63	8		T9	9		T72	8
valid_sources[0x5f]	3659	1			T67	1		T63	4		T30	1
valid_sources[0x60]	3804	1			T227	3		T63	5		T9	3
valid_sources[0x61]	3942	1			T67	1		T87	1		T63	15
valid_sources[0x62]	3160	1			T63	5		T9	40		T72	5
valid_sources[0x63]	3291	1			T63	7		T125	2		T25	1
valid_sources[0x64]	3461	1			T87	1		T63	19		T9	18
valid_sources[0x65]	3962	1			T6	2		T63	13		T9	1
valid_sources[0x66]	3288	1			T63	9		T9	26		T36	31
valid_sources[0x67]	3381	1			T67	1		T63	8		T9	10
valid_sources[0x68]	4369	1			T63	10		T9	35		T205	2
valid_sources[0x69]	3427	1			T46	2		T63	13		T9	5
valid_sources[0x6a]	3755	1			T63	16		T35	1		T30	1
valid_sources[0x6b]	3116	1			T63	12		T9	22		T72	18
valid_sources[0x6c]	3534	1			T63	11		T9	9		T72	11
valid_sources[0x6d]	3634	1			T63	10		T9	12		T37	3
valid_sources[0x6e]	3641	1			T73	1		T63	15		T9	4
valid_sources[0x6f]	3148	1			T63	8		T9	2		T72	20
valid_sources[0x70]	3747	1			T63	11		T9	13		T36	46
valid_sources[0x71]	3410	1			T63	8		T9	5		T72	9
valid_sources[0x72]	3436	1			T63	7		T9	14		T72	37
valid_sources[0x73]	3684	1			T63	10		T9	4		T72	2
valid_sources[0x74]	3489	1			T63	11		T9	14		T72	34
valid_sources[0x75]	3380	1			T67	2		T63	8		T9	11
valid_sources[0x76]	3957	1			T64	1		T71	1		T63	23
valid_sources[0x77]	3604	1			T63	17		T60	1		T9	5
valid_sources[0x78]	3581	1			T67	2		T63	7		T9	4
valid_sources[0x79]	3371	1			T63	9		T9	13		T72	12
valid_sources[0x7a]	3825	1			T12	1		T63	16		T25	1
valid_sources[0x7b]	5025	1			T67	2		T63	13		T25	2
valid_sources[0x7c]	3201	1			T63	6		T9	19		T72	1
valid_sources[0x7d]	4226	1			T63	14		T25	1		T9	23
valid_sources[0x7e]	3470	1			T71	1		T63	2		T9	9
valid_sources[0x7f]	3621	1			T29	2		T63	10		T9	18
valid_sources[0x80]	3467	1			T63	8		T61	1		T9	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

330265

1

T47

6

T45

2

T66

80

values[0x0]

all_enables

biggest_size

154583

1

T3

1

T86

1

T34

1

values[0x1]

all_enables

biggest_size

154869

1

T6

2

T14

1

T40

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8048	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

110755

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33057	1			T63	374		T9	478		T72	431
values[0x0]	41891	1			T2	1		T12	1		T13	1
values[0x1]	43855	1			T1	1		T3	1		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

113625

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	556	1			T202	2		T63	153		T30	2
valid_sources[0x01]	301	1			T72	4		T229	2		T230	1
valid_sources[0x02]	408	1			T44	1		T231	3		T80	23
valid_sources[0x03]	379	1			T87	3		T72	18		T36	1
valid_sources[0x04]	893	1			T72	20		T232	1		T233	6
valid_sources[0x05]	300	1			T72	9		T36	1		T80	18
valid_sources[0x06]	671	1			T31	1		T191	1		T72	13
valid_sources[0x07]	270	1			T9	2		T72	9		T234	1
valid_sources[0x08]	339	1			T235	1		T72	2		T229	2
valid_sources[0x09]	353	1			T72	10		T236	2		T237	8
valid_sources[0x0a]	362	1			T27	1		T63	2		T72	5
valid_sources[0x0b]	503	1			T125	1		T72	5		T232	6
valid_sources[0x0c]	328	1			T9	1		T72	4		T238	1
valid_sources[0x0d]	462	1			T47	1		T72	15		T36	171
valid_sources[0x0e]	425	1			T83	1		T53	2		T239	1
valid_sources[0x0f]	643	1			T63	144		T9	1		T72	1
valid_sources[0x10]	326	1			T122	1		T61	1		T72	2
valid_sources[0x11]	736	1			T72	13		T240	1		T36	1
valid_sources[0x12]	598	1			T97	1		T72	14		T241	4
valid_sources[0x13]	378	1			T72	9		T212	1		T80	19
valid_sources[0x14]	794	1			T22	1		T228	1		T72	16
valid_sources[0x15]	420	1			T174	1		T32	1		T9	3
valid_sources[0x16]	566	1			T123	1		T72	19		T242	2
valid_sources[0x17]	469	1			T62	1		T243	2		T72	3
valid_sources[0x18]	313	1			T200	1		T244	1		T9	1
valid_sources[0x19]	769	1			T9	2		T72	2		T245	1
valid_sources[0x1a]	339	1			T63	24		T72	10		T80	11
valid_sources[0x1b]	397	1			T85	1		T118	1		T63	76
valid_sources[0x1c]	700	1			T9	1		T72	2		T230	2
valid_sources[0x1d]	473	1			T31	1		T246	1		T205	1
valid_sources[0x1e]	392	1			T63	84		T72	1		T80	31
valid_sources[0x1f]	280	1			T247	1		T72	8		T229	1
valid_sources[0x20]	899	1			T59	1		T72	13		T246	1
valid_sources[0x21]	424	1			T9	56		T72	5		T245	1
valid_sources[0x22]	558	1			T63	18		T9	2		T72	2
valid_sources[0x23]	510	1			T63	1		T192	1		T72	4
valid_sources[0x24]	318	1			T41	8		T72	2		T80	7
valid_sources[0x25]	535	1			T72	4		T205	1		T36	2
valid_sources[0x26]	325	1			T72	10		T248	1		T36	1
valid_sources[0x27]	607	1			T139	1		T63	79		T72	2
valid_sources[0x28]	479	1			T9	38		T249	1		T250	1
valid_sources[0x29]	310	1			T251	18		T36	2		T80	22
valid_sources[0x2a]	672	1			T123	2		T72	17		T252	3
valid_sources[0x2b]	589	1			T72	2		T10	2		T240	1
valid_sources[0x2c]	310	1			T72	1		T229	1		T253	11
valid_sources[0x2d]	336	1			T9	58		T72	1		T205	1
valid_sources[0x2e]	514	1			T9	191		T72	1		T203	1
valid_sources[0x2f]	631	1			T72	9		T229	1		T36	33
valid_sources[0x30]	865	1			T13	1		T72	5		T36	3
valid_sources[0x31]	369	1			T32	1		T63	44		T72	2
valid_sources[0x32]	368	1			T52	5		T53	1		T254	1
valid_sources[0x33]	309	1			T9	1		T72	3		T229	1
valid_sources[0x34]	641	1			T255	1		T243	2		T72	4
valid_sources[0x35]	350	1			T193	1		T72	5		T238	1
valid_sources[0x36]	457	1			T72	6		T256	7		T80	28
valid_sources[0x37]	679	1			T71	5		T72	4		T36	91
valid_sources[0x38]	360	1			T72	6		T36	1		T80	22
valid_sources[0x39]	422	1			T123	1		T126	1		T72	2
valid_sources[0x3a]	779	1			T202	1		T9	1		T72	7
valid_sources[0x3b]	367	1			T9	1		T188	1		T192	1
valid_sources[0x3c]	635	1			T63	1		T61	2		T185	1
valid_sources[0x3d]	368	1			T51	1		T244	1		T189	1
valid_sources[0x3e]	430	1			T117	1		T123	4		T243	1
valid_sources[0x3f]	458	1			T63	1		T72	2		T257	1
valid_sources[0x40]	298	1			T63	1		T244	1		T9	1
valid_sources[0x41]	650	1			T23	2		T60	1		T72	5
valid_sources[0x42]	1024	1			T46	1		T9	1		T72	1
valid_sources[0x43]	717	1			T32	2		T63	283		T72	11
valid_sources[0x44]	410	1			T173	1		T31	1		T72	9
valid_sources[0x45]	332	1			T72	10		T36	15		T80	28
valid_sources[0x46]	426	1			T9	2		T72	2		T36	2
valid_sources[0x47]	414	1			T126	5		T72	3		T258	1
valid_sources[0x48]	320	1			T75	1		T76	1		T255	1
valid_sources[0x49]	447	1			T31	1		T72	13		T36	87
valid_sources[0x4a]	547	1			T63	2		T72	3		T259	2
valid_sources[0x4b]	347	1			T63	1		T72	4		T252	1
valid_sources[0x4c]	490	1			T55	2		T63	53		T260	6
valid_sources[0x4d]	384	1			T72	10		T261	1		T80	11
valid_sources[0x4e]	381	1			T8	1		T123	3		T9	43
valid_sources[0x4f]	423	1			T123	4		T9	3		T72	8
valid_sources[0x50]	327	1			T12	1		T244	1		T72	3
valid_sources[0x51]	476	1			T176	6		T9	1		T72	9
valid_sources[0x52]	439	1			T21	2		T9	1		T72	3
valid_sources[0x53]	978	1			T22	1		T74	1		T72	1
valid_sources[0x54]	291	1			T72	1		T262	1		T259	3
valid_sources[0x55]	586	1			T53	1		T87	4		T63	1
valid_sources[0x56]	452	1			T188	3		T72	4		T257	1
valid_sources[0x57]	680	1			T83	1		T123	1		T188	1
valid_sources[0x58]	521	1			T19	1		T63	6		T9	186
valid_sources[0x59]	436	1			T79	1		T175	16		T63	2
valid_sources[0x5a]	341	1			T202	1		T9	1		T72	12
valid_sources[0x5b]	342	1			T51	1		T192	1		T72	14
valid_sources[0x5c]	310	1			T18	1		T100	1		T263	1
valid_sources[0x5d]	303	1			T264	1		T72	2		T203	1
valid_sources[0x5e]	639	1			T9	1		T265	1		T266	1
valid_sources[0x5f]	376	1			T22	2		T243	2		T72	9
valid_sources[0x60]	739	1			T52	1		T53	1		T72	1
valid_sources[0x61]	354	1			T244	1		T72	9		T205	1
valid_sources[0x62]	631	1			T50	2		T267	1		T268	3
valid_sources[0x63]	515	1			T9	11		T72	6		T36	2
valid_sources[0x64]	251	1			T2	1		T72	3		T269	5
valid_sources[0x65]	504	1			T70	1		T72	10		T265	2
valid_sources[0x66]	623	1			T9	58		T72	5		T246	1
valid_sources[0x67]	375	1			T270	1		T244	1		T72	14
valid_sources[0x68]	497	1			T90	1		T123	1		T126	2
valid_sources[0x69]	433	1			T9	1		T72	6		T271	2
valid_sources[0x6a]	383	1			T63	3		T72	2		T267	1
valid_sources[0x6b]	285	1			T125	1		T72	3		T266	1
valid_sources[0x6c]	446	1			T26	1		T243	1		T9	3
valid_sources[0x6d]	484	1			T61	1		T72	10		T272	1
valid_sources[0x6e]	431	1			T72	4		T36	51		T80	15
valid_sources[0x6f]	335	1			T273	1		T72	6		T274	8
valid_sources[0x70]	516	1			T52	2		T72	11		T275	14
valid_sources[0x71]	315	1			T63	1		T189	1		T72	4
valid_sources[0x72]	333	1			T63	1		T9	2		T72	2
valid_sources[0x73]	361	1			T9	1		T72	1		T203	1
valid_sources[0x74]	329	1			T48	1		T52	2		T243	2
valid_sources[0x75]	401	1			T72	6		T276	1		T213	10
valid_sources[0x76]	367	1			T72	7		T10	2		T252	1
valid_sources[0x77]	338	1			T277	1		T278	1		T72	10
valid_sources[0x78]	609	1			T127	6		T72	7		T80	23
valid_sources[0x79]	502	1			T63	4		T125	1		T72	8
valid_sources[0x7a]	380	1			T72	7		T80	13		T82	27
valid_sources[0x7b]	396	1			T243	1		T72	5		T229	1
valid_sources[0x7c]	477	1			T53	1		T9	40		T72	9
valid_sources[0x7d]	476	1			T6	1		T279	1		T72	3
valid_sources[0x7e]	467	1			T63	2		T9	1		T192	1
valid_sources[0x7f]	625	1			T118	3		T177	8		T192	1
valid_sources[0x80]	794	1			T263	1		T9	290		T72	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29107

1

T63

350

T9

448

T72

406

values[0x0]

all_enables

biggest_size

40927

1

T2

1

T12

1

T13

1

values[0x1]

all_enables

biggest_size

40721

1

T1

1

T3

1

T6

1