Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

713205

1

T2

2

T12

3

T13

1

full_word

654434

1

T3

1

T6

2

T14

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1367339	1			T2	2		T3	1		T12	3
auto[TlIntgErrCmd]	111	1			T194	4		T179	1		T195	3
auto[TlIntgErrData]	101	1			T194	4		T179	5		T195	5
auto[TlIntgErrBoth]	88	1			T194	2		T179	4		T195	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

574377

1

T26

1

T14

1

T47

10

auto[1]

793262

1

T2

2

T3

1

T12

3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	242400	1			T26	1		T14	1		T47	4
auto[TlIntgErrNone]	partial	auto[1]	470533	1			T2	2		T12	3		T13	1
auto[TlIntgErrNone]	full_word	auto[0]	331837	1			T47	6		T45	2		T66	80
auto[TlIntgErrNone]	full_word	auto[1]	322569	1			T3	1		T6	2		T14	1
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T194	1		T195	3		T180	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T194	2		T179	1		T180	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T194	1		T214	1		T219	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T214	1		T222	1		T223	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T194	1		T179	3		T180	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T194	2		T179	2		T195	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T194	1		T217	1		T218	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T195	1		T214	1		T221	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T194	1		T179	1		T195	2
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T179	2		T180	1		T220	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T215	1		T224	1		T225	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T194	1		T179	1		T218	1