Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 135502105 138755 0 0
late_debug_enable_rd_A 135502105 8872 0 0
late_debug_enable_regwen_rd_A 135502105 8070 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 135502105 138755 0 0
T9 0 2267 0 0
T36 0 7146 0 0
T60 103633 0 0 0
T63 54878 1935 0 0
T72 0 1856 0 0
T77 0 8218 0 0
T80 0 5164 0 0
T81 0 7509 0 0
T82 0 5680 0 0
T119 0 9346 0 0
T120 0 14930 0 0
T121 390094 0 0 0
T122 185802 0 0 0
T123 13912 0 0 0
T124 575838 0 0 0
T125 75940 0 0 0
T126 1532 0 0 0
T127 32145 0 0 0
T128 64853 0 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 135502105 8872 0 0
T9 122125 881 0 0
T31 150730 0 0 0
T112 0 1119 0 0
T138 0 2 0 0
T178 0 5 0 0
T179 0 31 0 0
T180 0 31 0 0
T181 0 56 0 0
T182 0 27 0 0
T183 0 172 0 0
T184 0 154 0 0
T185 19648 0 0 0
T186 88336 0 0 0
T187 858258 0 0 0
T188 198686 0 0 0
T189 10024 0 0 0
T190 79862 0 0 0
T191 269476 0 0 0
T192 1296 0 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 135502105 8070 0 0
T9 122125 667 0 0
T31 150730 0 0 0
T112 0 883 0 0
T134 0 6 0 0
T138 0 1 0 0
T178 0 15 0 0
T179 0 37 0 0
T180 0 16 0 0
T181 0 85 0 0
T182 0 28 0 0
T183 0 123 0 0
T185 19648 0 0 0
T186 88336 0 0 0
T187 858258 0 0 0
T188 198686 0 0 0
T189 10024 0 0 0
T190 79862 0 0 0
T191 269476 0 0 0
T192 1296 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%