Line Coverage for Module :
prim_sparse_fsm_flop
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 40 | 1 | 1 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
ROUTINE | 47 | 4 | 4 | 100.00 |
39 );
40 1/1 assign state_o = StateEnumT'(state_raw);
Tests: T1 T2 T3
41
42 `ifdef INC_ASSERT
43 1/1 assign unused_err_o = is_undefined_state(state_o);
Tests: T1 T2 T3
44
45 function automatic logic is_undefined_state(StateEnumT sig);
46 // This is written with a vector in order to make it amenable to x-prop analysis.
47 1/1 logic is_defined = 1'b0;
Tests: T1 T2 T3
48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
Tests: T1 T2 T3
49 1/1 is_defined |= (sig === t);
Tests: T1 T2 T3
50 end
51 1/1 return ~is_defined;
Tests: T1 T2 T3
Assert Coverage for Module :
prim_sparse_fsm_flop
Assertion Details
AssertConnected_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
526 |
526 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T12 |
2 |
2 |
0 |
0 |
T13 |
2 |
2 |
0 |
0 |
T18 |
2 |
2 |
0 |
0 |
T26 |
2 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_state_regs
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 40 | 1 | 1 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
ROUTINE | 47 | 4 | 4 | 100.00 |
39 );
40 1/1 assign state_o = StateEnumT'(state_raw);
Tests: T1 T2 T3
41
42 `ifdef INC_ASSERT
43 1/1 assign unused_err_o = is_undefined_state(state_o);
Tests: T1 T2 T3
44
45 function automatic logic is_undefined_state(StateEnumT sig);
46 // This is written with a vector in order to make it amenable to x-prop analysis.
47 1/1 logic is_defined = 1'b0;
Tests: T1 T2 T3
48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
Tests: T1 T2 T3
49 1/1 is_defined |= (sig === t);
Tests: T1 T2 T3
50 end
51 1/1 return ~is_defined;
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_state_regs
Assertion Details
AssertConnected_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
263 |
263 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_state_regs
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 40 | 1 | 1 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
ROUTINE | 47 | 4 | 4 | 100.00 |
39 );
40 1/1 assign state_o = StateEnumT'(state_raw);
Tests: T1 T2 T3
41
42 `ifdef INC_ASSERT
43 1/1 assign unused_err_o = is_undefined_state(state_o);
Tests: T1 T2 T3
44
45 function automatic logic is_undefined_state(StateEnumT sig);
46 // This is written with a vector in order to make it amenable to x-prop analysis.
47 1/1 logic is_defined = 1'b0;
Tests: T1 T2 T3
48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin
Tests: T1 T2 T3
49 1/1 is_defined |= (sig === t);
Tests: T1 T2 T3
50 end
51 1/1 return ~is_defined;
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_state_regs
Assertion Details
AssertConnected_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
263 |
263 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |