Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reg_regs.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.78 100.00 93.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_regs


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 89.23 89.23
u_tlul_data_integ_dec 100.00 100.00 100.00



Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.78 100.00 93.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 97.92 98.11 95.24 100.00 i_tlul_adapter_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 89.23 89.23
u_tlul_data_integ_dec 100.00 100.00 100.00

Line Coverage for Module : tlul_cmd_intg_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00

21 tl_h2d_cmd_intg_t cmd; 22 1/1 assign cmd = extract_h2d_cmd_intg(tl_i); Tests: T1 T2 T3  23 24 prim_secded_inv_64_57_dec u_chk ( 25 .data_i({tl_i.a_user.cmd_intg, H2DCmdMaxWidth'(cmd)}), 26 .data_o(), 27 .syndrome_o(), 28 .err_o(err) 29 ); 30 31 tlul_data_integ_dec u_tlul_data_integ_dec ( 32 .data_intg_i({tl_i.a_user.data_intg, DataMaxWidth'(tl_i.a_data)}), 33 .data_err_o(data_err) 34 ); 35 36 // error output is transactional, it is up to the instantiating module 37 // to determine if a permanent latch is feasible 38 // [LOWRISC] err and data_err is unknown when a_valid is low, so we can't cover 39 // the condition coverage - (|err | (|data_err)) == 0/1, when a_valid = 0, which is 40 // fine as driving unknown is better. `err_o` is used as a condition in other places, 41 // which needs to be covered with 0 and 1, so it's OK to disable the entire coverage. 42 //VCS coverage off 43 // pragma coverage off 44 unreachable assign err_o = tl_i.a_valid & (|err | (|data_err)); 45 //VCS coverage on 46 // pragma coverage on 47 48 logic unused_tl; 49 1/1 assign unused_tl = |tl_i; Tests: T1 T2 T3 

Assert Coverage for Module : tlul_cmd_intg_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 746 746 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 746 746 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T12 2 2 0 0
T13 2 2 0 0
T18 2 2 0 0
T26 2 2 0 0

Line Coverage for Instance : tb.dut.u_reg_regs.u_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00

21 tl_h2d_cmd_intg_t cmd; 22 1/1 assign cmd = extract_h2d_cmd_intg(tl_i); Tests: T1 T2 T3  23 24 prim_secded_inv_64_57_dec u_chk ( 25 .data_i({tl_i.a_user.cmd_intg, H2DCmdMaxWidth'(cmd)}), 26 .data_o(), 27 .syndrome_o(), 28 .err_o(err) 29 ); 30 31 tlul_data_integ_dec u_tlul_data_integ_dec ( 32 .data_intg_i({tl_i.a_user.data_intg, DataMaxWidth'(tl_i.a_data)}), 33 .data_err_o(data_err) 34 ); 35 36 // error output is transactional, it is up to the instantiating module 37 // to determine if a permanent latch is feasible 38 // [LOWRISC] err and data_err is unknown when a_valid is low, so we can't cover 39 // the condition coverage - (|err | (|data_err)) == 0/1, when a_valid = 0, which is 40 // fine as driving unknown is better. `err_o` is used as a condition in other places, 41 // which needs to be covered with 0 and 1, so it's OK to disable the entire coverage. 42 //VCS coverage off 43 // pragma coverage off 44 unreachable assign err_o = tl_i.a_valid & (|err | (|data_err)); 45 //VCS coverage on 46 // pragma coverage on 47 48 logic unused_tl; 49 1/1 assign unused_tl = |tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_reg_regs.u_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 483 483 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 483 483 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T26 1 1 0 0

Line Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2211100.00
CONT_ASSIGN4400
CONT_ASSIGN4911100.00

21 tl_h2d_cmd_intg_t cmd; 22 1/1 assign cmd = extract_h2d_cmd_intg(tl_i); Tests: T1 T2 T3  23 24 prim_secded_inv_64_57_dec u_chk ( 25 .data_i({tl_i.a_user.cmd_intg, H2DCmdMaxWidth'(cmd)}), 26 .data_o(), 27 .syndrome_o(), 28 .err_o(err) 29 ); 30 31 tlul_data_integ_dec u_tlul_data_integ_dec ( 32 .data_intg_i({tl_i.a_user.data_intg, DataMaxWidth'(tl_i.a_data)}), 33 .data_err_o(data_err) 34 ); 35 36 // error output is transactional, it is up to the instantiating module 37 // to determine if a permanent latch is feasible 38 // [LOWRISC] err and data_err is unknown when a_valid is low, so we can't cover 39 // the condition coverage - (|err | (|data_err)) == 0/1, when a_valid = 0, which is 40 // fine as driving unknown is better. `err_o` is used as a condition in other places, 41 // which needs to be covered with 0 and 1, so it's OK to disable the entire coverage. 42 //VCS coverage off 43 // pragma coverage off 44 unreachable assign err_o = tl_i.a_valid & (|err | (|data_err)); 45 //VCS coverage on 46 // pragma coverage on 47 48 logic unused_tl; 49 1/1 assign unused_tl = |tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PayLoadWidthCheck 263 263 0 0


PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 263 263 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T18 1 1 0 0
T26 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%