Unified Coverage Report :: Module :: prim_fifo_async_simple

Module : prim_fifo_async_simple

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	93.75			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_simple.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.dap.i_dmi_cdc.i_cdc_resp	97.78	100.00	93.33			100.00
tb.dut.dap.i_dmi_cdc.i_cdc_req	97.92	100.00	93.75			100.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.78	100.00	93.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.93	100.00	85.71			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	79.17	100.00	66.67			100.00	50.00

---

Module Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	93.75			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.09	100.00	86.36			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		i_dmi_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	79.17	100.00	66.67			100.00	50.00

Line Coverage for Module : prim_fifo_async_simple

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	5	5	100.00
ALWAYS	85	2	2	100.00
CONT_ASSIGN	89	1	1	100.00

38                        logic pending_d, pending_q, not_in_reset_q;
39         1/1            assign wready_o = !pending_q && not_in_reset_q;
           Tests:       T1 T2 T3 
40         1/1            assign wr_en = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
41         1/1            assign src_req = pending_q || wvalid_i;
           Tests:       T1 T2 T3 
42                      
43         1/1            assign pending_d = (src_ack)  ? 1'b0 :
           Tests:       T1 T2 T3 
44                                           (wr_en)    ? 1'b1 : pending_q;
45                      
46                        logic dst_req, dst_ack;
47         1/1            assign rvalid_o = dst_req;
           Tests:       T1 T2 T3 
48         1/1            assign dst_ack = dst_req && rready_i;
           Tests:       T1 T2 T3 
49                      
50                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
51         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
52         1/1                pending_q <= 1'b0;
           Tests:       T1 T2 T3 
53         1/1                not_in_reset_q <= 1'b0;
           Tests:       T1 T2 T3 
54                          end else begin
55         1/1                pending_q <= pending_d;
           Tests:       T1 T2 T3 
56         1/1                not_in_reset_q <= 1'b1;
           Tests:       T1 T2 T3 
57                          end
58                        end
59                      
60                        ////////////////////////////////////
61                        // REQ/ACK synchronizer primitive //
62                        ////////////////////////////////////
63                      
64                        prim_sync_reqack #(
65                          .EnRstChks(EnRstChks),
66                          .EnRzHs(EnRzHs)
67                        ) u_prim_sync_reqack (
68                          .clk_src_i(clk_wr_i),
69                          .rst_src_ni(rst_wr_ni),
70                          .clk_dst_i(clk_rd_i),
71                          .rst_dst_ni(rst_rd_ni),
72                          .req_chk_i(1'b0),
73                          .src_req_i(src_req),
74                          .src_ack_o(src_ack),
75                          .dst_req_o(dst_req),
76                          .dst_ack_i(dst_ack)
77                        );
78                      
79                        //////////////////////
80                        // Data holding reg //
81                        //////////////////////
82                      
83                        logic [Width-1:0] data_q;
84                        always_ff @(posedge clk_wr_i) begin
85         1/1              if (wr_en) begin
           Tests:       T1 T2 T3 
86         1/1                data_q <= wdata_i;
           Tests:       T1 T2 T3 
87                          end
                        MISSING_ELSE
88                        end
89         1/1            assign rdata_o = data_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_fifo_async_simple

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!pending_q)) && not_in_reset_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (pending_q || wvalid_i)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       43
 SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
                 --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (dst_req && rready_i)
             ---1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T116
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_async_simple

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	43	3	3	100.00
IF	51	2	2	100.00
IF	85	2	2	100.00

43           assign pending_d = (src_ack)  ? 1'b0 :
                                           -1-  
                                           ==>  
44                              (wr_en)    ? 1'b1 : pending_q;
                                           -2-  
                                           ==>  
                                           ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

51             if (!rst_wr_ni) begin
               -1-  
52               pending_q <= 1'b0;
                 ==>
53               not_in_reset_q <= 1'b0;
54             end else begin
55               pending_q <= pending_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

85             if (wr_en) begin
               -1-  
86               data_q <= wdata_i;
                 ==>
87             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	5	5	100.00
ALWAYS	85	2	2	100.00
CONT_ASSIGN	89	1	1	100.00

38                        logic pending_d, pending_q, not_in_reset_q;
39         1/1            assign wready_o = !pending_q && not_in_reset_q;
           Tests:       T1 T2 T3 
40         1/1            assign wr_en = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
41         1/1            assign src_req = pending_q || wvalid_i;
           Tests:       T1 T2 T3 
42                      
43         1/1            assign pending_d = (src_ack)  ? 1'b0 :
           Tests:       T1 T2 T3 
44                                           (wr_en)    ? 1'b1 : pending_q;
45                      
46                        logic dst_req, dst_ack;
47         1/1            assign rvalid_o = dst_req;
           Tests:       T1 T2 T3 
48         1/1            assign dst_ack = dst_req && rready_i;
           Tests:       T1 T2 T3 
49                      
50                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
51         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
52         1/1                pending_q <= 1'b0;
           Tests:       T1 T2 T3 
53         1/1                not_in_reset_q <= 1'b0;
           Tests:       T1 T2 T3 
54                          end else begin
55         1/1                pending_q <= pending_d;
           Tests:       T1 T2 T3 
56         1/1                not_in_reset_q <= 1'b1;
           Tests:       T1 T2 T3 
57                          end
58                        end
59                      
60                        ////////////////////////////////////
61                        // REQ/ACK synchronizer primitive //
62                        ////////////////////////////////////
63                      
64                        prim_sync_reqack #(
65                          .EnRstChks(EnRstChks),
66                          .EnRzHs(EnRzHs)
67                        ) u_prim_sync_reqack (
68                          .clk_src_i(clk_wr_i),
69                          .rst_src_ni(rst_wr_ni),
70                          .clk_dst_i(clk_rd_i),
71                          .rst_dst_ni(rst_rd_ni),
72                          .req_chk_i(1'b0),
73                          .src_req_i(src_req),
74                          .src_ack_o(src_ack),
75                          .dst_req_o(dst_req),
76                          .dst_ack_i(dst_ack)
77                        );
78                      
79                        //////////////////////
80                        // Data holding reg //
81                        //////////////////////
82                      
83                        logic [Width-1:0] data_q;
84                        always_ff @(posedge clk_wr_i) begin
85         1/1              if (wr_en) begin
           Tests:       T1 T2 T3 
86         1/1                data_q <= wdata_i;
           Tests:       T1 T2 T3 
87                          end
                        MISSING_ELSE
88                        end
89         1/1            assign rdata_o = data_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!pending_q)) && not_in_reset_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (pending_q || wvalid_i)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       43
 SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
                 --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (dst_req && rready_i)
             ---1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_resp

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	43	3	3	100.00
IF	51	2	2	100.00
IF	85	2	2	100.00

43           assign pending_d = (src_ack)  ? 1'b0 :
                                           -1-  
                                           ==>  
44                              (wr_en)    ? 1'b1 : pending_q;
                                           -2-  
                                           ==>  
                                           ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

51             if (!rst_wr_ni) begin
               -1-  
52               pending_q <= 1'b0;
                 ==>
53               not_in_reset_q <= 1'b0;
54             end else begin
55               pending_q <= pending_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

85             if (wr_en) begin
               -1-  
86               data_q <= wdata_i;
                 ==>
87             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	40	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	51	5	5	100.00
ALWAYS	85	2	2	100.00
CONT_ASSIGN	89	1	1	100.00

38                        logic pending_d, pending_q, not_in_reset_q;
39         1/1            assign wready_o = !pending_q && not_in_reset_q;
           Tests:       T1 T2 T3 
40         1/1            assign wr_en = wvalid_i && wready_o;
           Tests:       T1 T2 T3 
41         1/1            assign src_req = pending_q || wvalid_i;
           Tests:       T1 T2 T3 
42                      
43         1/1            assign pending_d = (src_ack)  ? 1'b0 :
           Tests:       T1 T2 T3 
44                                           (wr_en)    ? 1'b1 : pending_q;
45                      
46                        logic dst_req, dst_ack;
47         1/1            assign rvalid_o = dst_req;
           Tests:       T1 T2 T3 
48         1/1            assign dst_ack = dst_req && rready_i;
           Tests:       T1 T2 T3 
49                      
50                        always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
51         1/1              if (!rst_wr_ni) begin
           Tests:       T1 T2 T3 
52         1/1                pending_q <= 1'b0;
           Tests:       T1 T2 T3 
53         1/1                not_in_reset_q <= 1'b0;
           Tests:       T1 T2 T3 
54                          end else begin
55         1/1                pending_q <= pending_d;
           Tests:       T1 T2 T3 
56         1/1                not_in_reset_q <= 1'b1;
           Tests:       T1 T2 T3 
57                          end
58                        end
59                      
60                        ////////////////////////////////////
61                        // REQ/ACK synchronizer primitive //
62                        ////////////////////////////////////
63                      
64                        prim_sync_reqack #(
65                          .EnRstChks(EnRstChks),
66                          .EnRzHs(EnRzHs)
67                        ) u_prim_sync_reqack (
68                          .clk_src_i(clk_wr_i),
69                          .rst_src_ni(rst_wr_ni),
70                          .clk_dst_i(clk_rd_i),
71                          .rst_dst_ni(rst_rd_ni),
72                          .req_chk_i(1'b0),
73                          .src_req_i(src_req),
74                          .src_ack_o(src_ack),
75                          .dst_req_o(dst_req),
76                          .dst_ack_i(dst_ack)
77                        );
78                      
79                        //////////////////////
80                        // Data holding reg //
81                        //////////////////////
82                      
83                        logic [Width-1:0] data_q;
84                        always_ff @(posedge clk_wr_i) begin
85         1/1              if (wr_en) begin
           Tests:       T1 T2 T3 
86         1/1                data_q <= wdata_i;
           Tests:       T1 T2 T3 
87                          end
                        MISSING_ELSE
88                        end
89         1/1            assign rdata_o = data_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!pending_q)) && not_in_reset_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (pending_q || wvalid_i)
             ----1----    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (src_ack ? 1'b0 : (wr_en ? 1'b1 : pending_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       43
 SUB-EXPRESSION (wr_en ? 1'b1 : pending_q)
                 --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       48
 EXPRESSION (dst_req && rready_i)
             ---1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T116
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.dap.i_dmi_cdc.i_cdc_req

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	43	3	3	100.00
IF	51	2	2	100.00
IF	85	2	2	100.00

43           assign pending_d = (src_ack)  ? 1'b0 :
                                           -1-  
                                           ==>  
44                              (wr_en)    ? 1'b1 : pending_q;
                                           -2-  
                                           ==>  
                                           ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

51             if (!rst_wr_ni) begin
               -1-  
52               pending_q <= 1'b0;
                 ==>
53               not_in_reset_q <= 1'b0;
54             end else begin
55               pending_q <= pending_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

85             if (wr_en) begin
               -1-  
86               data_q <= wdata_i;
                 ==>
87             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3