Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7924466 7922974 0 0
selKnown1 76519465 76517973 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7924466 7922974 0 0
T1 11226 11224 0 0
T2 1848 1846 0 0
T3 1938 1936 0 0
T4 792 790 0 0
T5 3006 3002 0 0
T6 726 724 0 0
T7 3 1 0 0
T8 4 2 0 0
T12 2640 2638 0 0
T13 1044 1042 0 0
T14 2 0 0 0
T18 20964 20960 0 0
T24 2 0 0 0
T26 1600 1598 0 0
T41 0 7 0 0
T45 2 0 0 0
T47 2 0 0 0
T49 11 9 0 0
T50 0 2 0 0
T54 0 10 0 0
T66 2 0 0 0
T75 0 2 0 0
T76 0 1 0 0
T78 0 1 0 0
T99 0 1 0 0
T193 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 76519465 76517973 0 0
T1 15757 15755 0 0
T2 5728 5726 0 0
T3 14362 14360 0 0
T4 3607 3605 0 0
T5 33877 33873 0 0
T6 6124 6122 0 0
T7 2 0 0 0
T8 2 0 0 0
T12 18219 18217 0 0
T13 10189 10187 0 0
T14 2 0 0 0
T18 71725 71721 0 0
T21 0 8 0 0
T24 2 0 0 0
T26 24924 24922 0 0
T41 0 6 0 0
T45 2 0 0 0
T47 2 0 0 0
T49 10 8 0 0
T50 0 2 0 0
T54 0 20 0 0
T55 0 2 0 0
T66 2 0 0 0
T83 0 2 0 0
T88 0 40 0 0
T89 0 20 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2388021 2387758 0 0
selKnown1 70983114 70982851 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2388021 2387758 0 0
T1 5613 5612 0 0
T2 924 923 0 0
T3 969 968 0 0
T4 396 395 0 0
T5 1502 1501 0 0
T6 363 362 0 0
T12 1320 1319 0 0
T13 522 521 0 0
T18 10478 10477 0 0
T26 800 799 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 70983114 70982851 0 0
T1 10144 10143 0 0
T2 4804 4803 0 0
T3 13393 13392 0 0
T4 3211 3210 0 0
T5 32373 32372 0 0
T6 5761 5760 0 0
T12 16899 16898 0 0
T13 9667 9666 0 0
T18 61239 61238 0 0
T26 24124 24123 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 796 533 0 0
selKnown1 756 493 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 796 533 0 0
T5 1 0 0 0
T7 1 0 0 0
T8 2 1 0 0
T14 1 0 0 0
T18 4 3 0 0
T24 1 0 0 0
T41 0 3 0 0
T45 1 0 0 0
T47 1 0 0 0
T49 5 4 0 0
T50 0 1 0 0
T54 0 10 0 0
T55 0 1 0 0
T66 1 0 0 0
T75 0 1 0 0
T76 0 1 0 0
T193 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 756 493 0 0
T5 1 0 0 0
T7 1 0 0 0
T8 1 0 0 0
T14 1 0 0 0
T18 4 3 0 0
T21 0 4 0 0
T24 1 0 0 0
T41 0 3 0 0
T45 1 0 0 0
T47 1 0 0 0
T49 5 4 0 0
T50 0 1 0 0
T54 0 10 0 0
T55 0 1 0 0
T66 1 0 0 0
T83 0 1 0 0
T88 0 20 0 0
T89 0 10 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 5533895 5533412 0 0
selKnown1 5533895 5533412 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 5533895 5533412 0 0
T1 5613 5612 0 0
T2 924 923 0 0
T3 969 968 0 0
T4 396 395 0 0
T5 1502 1501 0 0
T6 363 362 0 0
T12 1320 1319 0 0
T13 522 521 0 0
T18 10478 10477 0 0
T26 800 799 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 5533895 5533412 0 0
T1 5613 5612 0 0
T2 924 923 0 0
T3 969 968 0 0
T4 396 395 0 0
T5 1502 1501 0 0
T6 363 362 0 0
T12 1320 1319 0 0
T13 522 521 0 0
T18 10478 10477 0 0
T26 800 799 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT99
11CoveredT99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT99
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1754 1271 0 0
selKnown1 1700 1217 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1754 1271 0 0
T5 1 0 0 0
T7 2 1 0 0
T8 2 1 0 0
T14 1 0 0 0
T18 4 3 0 0
T24 1 0 0 0
T41 0 4 0 0
T45 1 0 0 0
T47 1 0 0 0
T49 6 5 0 0
T50 0 1 0 0
T66 1 0 0 0
T75 0 1 0 0
T78 0 1 0 0
T99 0 1 0 0
T193 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1700 1217 0 0
T5 1 0 0 0
T7 1 0 0 0
T8 1 0 0 0
T14 1 0 0 0
T18 4 3 0 0
T21 0 4 0 0
T24 1 0 0 0
T41 0 3 0 0
T45 1 0 0 0
T47 1 0 0 0
T49 5 4 0 0
T50 0 1 0 0
T54 0 10 0 0
T55 0 1 0 0
T66 1 0 0 0
T83 0 1 0 0
T88 0 20 0 0
T89 0 10 0 0

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