Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts


Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 272383 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 601710 1 T14 1 T7 2 T15 3



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 496271 1 T14 1 T15 3 T44 3
values[0x0] 159818 1 T1 1 T3 1 T7 2
values[0x1] 218004 1 T3 2 T13 1 T14 2



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 180805 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 693288 1 T14 2 T7 2 T15 4



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3299 1 T29 2 T62 2 T34 25
valid_sources[0x01] 3601 1 T63 2 T34 25 T71 43
valid_sources[0x02] 3953 1 T65 1 T34 7 T71 22
valid_sources[0x03] 3050 1 T34 15 T71 19 T72 27
valid_sources[0x04] 3320 1 T63 1 T10 2 T34 24
valid_sources[0x05] 2966 1 T34 41 T71 39 T72 14
valid_sources[0x06] 3192 1 T44 1 T95 2 T34 14
valid_sources[0x07] 3516 1 T63 1 T32 1 T34 25
valid_sources[0x08] 3155 1 T34 31 T71 36 T72 20
valid_sources[0x09] 3466 1 T44 1 T217 2 T34 36
valid_sources[0x0a] 3264 1 T34 24 T71 28 T72 24
valid_sources[0x0b] 3458 1 T52 1 T34 48 T71 53
valid_sources[0x0c] 3513 1 T34 23 T71 32 T72 31
valid_sources[0x0d] 3387 1 T62 2 T59 2 T34 42
valid_sources[0x0e] 3723 1 T34 30 T16 1 T71 35
valid_sources[0x0f] 2821 1 T34 22 T205 1 T71 33
valid_sources[0x10] 3523 1 T88 1 T34 22 T33 1
valid_sources[0x11] 3487 1 T62 11 T28 1 T34 20
valid_sources[0x12] 2819 1 T34 27 T71 30 T218 3
valid_sources[0x13] 3138 1 T34 26 T16 1 T71 34
valid_sources[0x14] 3376 1 T32 1 T34 32 T71 29
valid_sources[0x15] 4011 1 T59 1 T34 17 T71 38
valid_sources[0x16] 3515 1 T57 1 T34 33 T16 1
valid_sources[0x17] 3018 1 T34 26 T71 34 T72 52
valid_sources[0x18] 2800 1 T34 39 T219 1 T80 1
valid_sources[0x19] 3378 1 T15 1 T133 1 T63 1
valid_sources[0x1a] 2887 1 T34 21 T71 27 T72 34
valid_sources[0x1b] 3256 1 T56 1 T63 1 T34 32
valid_sources[0x1c] 3453 1 T34 21 T71 22 T72 29
valid_sources[0x1d] 3696 1 T3 3 T63 1 T10 1
valid_sources[0x1e] 3312 1 T65 2 T69 1 T10 1
valid_sources[0x1f] 2972 1 T77 2 T34 33 T219 1
valid_sources[0x20] 2605 1 T63 1 T34 23 T71 23
valid_sources[0x21] 2773 1 T34 43 T35 1 T71 23
valid_sources[0x22] 3479 1 T62 3 T34 20 T71 24
valid_sources[0x23] 3169 1 T44 1 T34 22 T198 5
valid_sources[0x24] 3039 1 T34 22 T71 43 T72 43
valid_sources[0x25] 2849 1 T64 3 T34 42 T35 1
valid_sources[0x26] 3276 1 T34 42 T71 36 T220 1
valid_sources[0x27] 3260 1 T34 21 T71 29 T221 1
valid_sources[0x28] 3099 1 T34 32 T71 27 T72 27
valid_sources[0x29] 3351 1 T34 5 T71 27 T72 22
valid_sources[0x2a] 3980 1 T34 32 T71 31 T18 1
valid_sources[0x2b] 3220 1 T58 1 T34 26 T71 35
valid_sources[0x2c] 3479 1 T34 27 T71 28 T17 2
valid_sources[0x2d] 3116 1 T34 31 T196 1 T16 1
valid_sources[0x2e] 3460 1 T88 1 T34 15 T71 33
valid_sources[0x2f] 3676 1 T13 1 T34 28 T71 40
valid_sources[0x30] 3355 1 T34 14 T71 29 T72 15
valid_sources[0x31] 3432 1 T34 46 T71 42 T221 1
valid_sources[0x32] 3391 1 T63 1 T34 38 T80 1
valid_sources[0x33] 3656 1 T63 1 T34 19 T16 1
valid_sources[0x34] 3436 1 T56 2 T34 37 T71 31
valid_sources[0x35] 3396 1 T34 16 T71 32 T17 1
valid_sources[0x36] 2948 1 T70 2 T34 20 T71 27
valid_sources[0x37] 3090 1 T63 1 T34 19 T80 1
valid_sources[0x38] 2973 1 T34 27 T26 1 T71 37
valid_sources[0x39] 3412 1 T63 2 T34 21 T71 50
valid_sources[0x3a] 3553 1 T14 3 T34 35 T71 29
valid_sources[0x3b] 3197 1 T34 21 T71 24 T72 33
valid_sources[0x3c] 2913 1 T42 2 T34 30 T71 35
valid_sources[0x3d] 4814 1 T34 24 T201 1 T71 29
valid_sources[0x3e] 3122 1 T60 1 T58 1 T34 34
valid_sources[0x3f] 3627 1 T1 1 T63 1 T95 1
valid_sources[0x40] 3072 1 T34 11 T71 26 T218 4
valid_sources[0x41] 3300 1 T34 23 T71 42 T222 2
valid_sources[0x42] 3335 1 T63 1 T34 29 T201 1
valid_sources[0x43] 3881 1 T63 1 T34 26 T71 27
valid_sources[0x44] 2796 1 T34 17 T71 24 T223 1
valid_sources[0x45] 3343 1 T34 32 T71 38 T72 35
valid_sources[0x46] 3862 1 T34 22 T71 35 T72 33
valid_sources[0x47] 3255 1 T57 1 T34 19 T36 3
valid_sources[0x48] 2881 1 T34 37 T71 30 T72 29
valid_sources[0x49] 3258 1 T60 1 T34 25 T71 40
valid_sources[0x4a] 3150 1 T63 1 T58 1 T34 26
valid_sources[0x4b] 4326 1 T34 40 T80 1 T71 43
valid_sources[0x4c] 3196 1 T7 1 T63 1 T34 20
valid_sources[0x4d] 2988 1 T6 2 T34 33 T224 1
valid_sources[0x4e] 3136 1 T28 1 T10 1 T34 35
valid_sources[0x4f] 3049 1 T188 3 T34 17 T80 1
valid_sources[0x50] 3032 1 T34 33 T80 1 T71 27
valid_sources[0x51] 3007 1 T59 1 T34 26 T71 47
valid_sources[0x52] 3101 1 T34 41 T71 24 T72 34
valid_sources[0x53] 3968 1 T34 30 T71 27 T72 32
valid_sources[0x54] 3204 1 T62 19 T34 29 T11 1
valid_sources[0x55] 3606 1 T63 2 T178 1 T34 27
valid_sources[0x56] 2973 1 T63 1 T34 36 T71 25
valid_sources[0x57] 3133 1 T20 1 T60 1 T34 16
valid_sources[0x58] 3242 1 T44 1 T34 23 T71 28
valid_sources[0x59] 3226 1 T28 1 T34 37 T71 36
valid_sources[0x5a] 3097 1 T63 2 T58 1 T34 33
valid_sources[0x5b] 3315 1 T63 2 T34 31 T225 5
valid_sources[0x5c] 3041 1 T63 1 T34 41 T71 22
valid_sources[0x5d] 3022 1 T34 35 T196 1 T71 48
valid_sources[0x5e] 3358 1 T34 24 T71 29 T72 25
valid_sources[0x5f] 2975 1 T32 1 T34 23 T71 31
valid_sources[0x60] 3527 1 T59 2 T34 52 T67 4
valid_sources[0x61] 4352 1 T34 28 T71 39 T17 2
valid_sources[0x62] 3442 1 T28 1 T34 32 T80 1
valid_sources[0x63] 3497 1 T34 26 T71 34 T72 49
valid_sources[0x64] 3823 1 T63 1 T34 26 T80 1
valid_sources[0x65] 2858 1 T34 32 T71 36 T72 14
valid_sources[0x66] 3171 1 T28 2 T34 22 T71 28
valid_sources[0x67] 3370 1 T15 2 T34 22 T71 28
valid_sources[0x68] 7832 1 T34 42 T71 27 T72 36
valid_sources[0x69] 3093 1 T60 1 T34 20 T35 1
valid_sources[0x6a] 3234 1 T64 3 T34 12 T71 31
valid_sources[0x6b] 4087 1 T34 42 T71 40 T72 28
valid_sources[0x6c] 3135 1 T34 27 T71 28 T221 1
valid_sources[0x6d] 3117 1 T34 24 T195 6 T71 36
valid_sources[0x6e] 3379 1 T63 1 T188 1 T34 33
valid_sources[0x6f] 3028 1 T63 1 T65 1 T34 23
valid_sources[0x70] 3659 1 T34 24 T80 1 T71 22
valid_sources[0x71] 3022 1 T58 1 T34 19 T219 1
valid_sources[0x72] 4292 1 T63 1 T34 27 T226 2
valid_sources[0x73] 3353 1 T34 29 T219 1 T71 24
valid_sources[0x74] 4094 1 T34 37 T71 23 T72 44
valid_sources[0x75] 3755 1 T63 1 T34 44 T71 36
valid_sources[0x76] 3464 1 T34 31 T71 17 T17 2
valid_sources[0x77] 3330 1 T34 43 T71 31 T72 20
valid_sources[0x78] 3032 1 T56 1 T34 27 T71 31
valid_sources[0x79] 3070 1 T44 1 T56 1 T69 1
valid_sources[0x7a] 3554 1 T63 1 T65 1 T96 1
valid_sources[0x7b] 3577 1 T34 32 T197 4 T71 36
valid_sources[0x7c] 2787 1 T69 1 T34 23 T33 1
valid_sources[0x7d] 3148 1 T34 20 T35 2 T71 44
valid_sources[0x7e] 3028 1 T34 35 T71 34 T72 19
valid_sources[0x7f] 3288 1 T60 1 T34 16 T71 25
valid_sources[0x80] 3906 1 T37 1 T63 2 T34 22



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 297755 1 T15 1 T44 1 T6 1
values[0x0] all_enables biggest_size 152195 1 T7 2 T15 1 T44 3
values[0x1] all_enables biggest_size 151760 1 T14 1 T15 1 T29 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 8579 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 107728 1 T1 1 T2 1 T3 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 32604 1 T34 1004 T71 1371 T72 788
values[0x0] 40741 1 T2 1 T14 1 T7 1
values[0x1] 42962 1 T1 1 T3 1 T13 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5555 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 110752 1 T1 1 T2 1 T3 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 414 1 T71 10 T17 2 T218 1
valid_sources[0x01] 467 1 T34 97 T227 1 T71 13
valid_sources[0x02] 356 1 T22 1 T228 1 T71 14
valid_sources[0x03] 801 1 T34 18 T71 17 T229 1
valid_sources[0x04] 707 1 T230 1 T188 1 T128 1
valid_sources[0x05] 307 1 T122 1 T71 24 T72 15
valid_sources[0x06] 475 1 T231 1 T232 1 T34 2
valid_sources[0x07] 690 1 T123 1 T233 1 T234 8
valid_sources[0x08] 485 1 T34 191 T71 28 T235 1
valid_sources[0x09] 444 1 T27 1 T80 1 T236 1
valid_sources[0x0a] 577 1 T34 43 T71 16 T72 9
valid_sources[0x0b] 264 1 T34 1 T71 29 T72 29
valid_sources[0x0c] 334 1 T34 4 T80 1 T71 11
valid_sources[0x0d] 401 1 T237 1 T71 20 T72 8
valid_sources[0x0e] 303 1 T23 2 T71 28 T72 13
valid_sources[0x0f] 489 1 T238 1 T239 1 T240 1
valid_sources[0x10] 235 1 T76 1 T71 19 T72 16
valid_sources[0x11] 383 1 T177 1 T34 1 T225 1
valid_sources[0x12] 341 1 T34 87 T71 6 T72 20
valid_sources[0x13] 350 1 T34 5 T71 26 T72 6
valid_sources[0x14] 269 1 T34 1 T71 29 T72 8
valid_sources[0x15] 309 1 T241 1 T242 1 T71 21
valid_sources[0x16] 316 1 T30 1 T34 1 T243 2
valid_sources[0x17] 466 1 T34 1 T228 1 T244 1
valid_sources[0x18] 483 1 T244 1 T201 1 T71 10
valid_sources[0x19] 335 1 T1 1 T31 2 T70 1
valid_sources[0x1a] 594 1 T34 140 T236 2 T71 13
valid_sources[0x1b] 390 1 T71 18 T72 12 T116 6
valid_sources[0x1c] 394 1 T81 1 T34 66 T25 1
valid_sources[0x1d] 665 1 T80 2 T71 11 T17 2
valid_sources[0x1e] 501 1 T243 2 T239 1 T71 32
valid_sources[0x1f] 551 1 T32 1 T245 1 T71 19
valid_sources[0x20] 469 1 T34 10 T228 1 T71 31
valid_sources[0x21] 385 1 T246 1 T71 18 T72 18
valid_sources[0x22] 476 1 T103 1 T245 2 T34 10
valid_sources[0x23] 492 1 T34 1 T236 1 T71 27
valid_sources[0x24] 460 1 T195 7 T71 17 T72 14
valid_sources[0x25] 246 1 T90 1 T58 1 T34 1
valid_sources[0x26] 541 1 T247 1 T248 1 T71 17
valid_sources[0x27] 468 1 T249 1 T189 1 T239 1
valid_sources[0x28] 357 1 T34 1 T201 2 T71 42
valid_sources[0x29] 256 1 T34 1 T71 14 T72 13
valid_sources[0x2a] 443 1 T21 1 T34 1 T71 20
valid_sources[0x2b] 304 1 T71 19 T72 31 T116 20
valid_sources[0x2c] 441 1 T250 4 T251 1 T71 28
valid_sources[0x2d] 497 1 T97 2 T34 1 T252 2
valid_sources[0x2e] 352 1 T253 8 T130 1 T71 23
valid_sources[0x2f] 438 1 T34 1 T251 1 T187 1
valid_sources[0x30] 421 1 T29 1 T254 1 T245 1
valid_sources[0x31] 525 1 T128 1 T233 1 T71 26
valid_sources[0x32] 660 1 T34 124 T71 9 T72 17
valid_sources[0x33] 400 1 T191 2 T34 3 T71 16
valid_sources[0x34] 497 1 T46 1 T56 1 T255 6
valid_sources[0x35] 381 1 T256 1 T71 31 T257 1
valid_sources[0x36] 274 1 T21 1 T188 1 T95 2
valid_sources[0x37] 711 1 T2 1 T236 2 T71 5
valid_sources[0x38] 628 1 T28 1 T201 1 T71 17
valid_sources[0x39] 338 1 T255 2 T71 40 T229 1
valid_sources[0x3a] 436 1 T15 1 T34 62 T237 1
valid_sources[0x3b] 442 1 T34 1 T224 2 T71 17
valid_sources[0x3c] 398 1 T19 1 T23 1 T71 34
valid_sources[0x3d] 576 1 T3 1 T5 1 T34 2
valid_sources[0x3e] 313 1 T71 31 T72 16 T258 4
valid_sources[0x3f] 531 1 T34 3 T237 1 T193 2
valid_sources[0x40] 744 1 T34 125 T259 4 T71 17
valid_sources[0x41] 529 1 T146 1 T34 1 T71 14
valid_sources[0x42] 270 1 T19 1 T71 26 T72 14
valid_sources[0x43] 390 1 T71 19 T260 3 T72 23
valid_sources[0x44] 291 1 T32 2 T85 1 T34 1
valid_sources[0x45] 242 1 T127 1 T71 22 T72 8
valid_sources[0x46] 785 1 T34 1 T71 15 T72 5
valid_sources[0x47] 635 1 T204 1 T34 1 T36 2
valid_sources[0x48] 296 1 T26 2 T71 24 T220 1
valid_sources[0x49] 443 1 T68 1 T228 1 T199 4
valid_sources[0x4a] 440 1 T19 1 T261 1 T71 44
valid_sources[0x4b] 534 1 T71 7 T72 7 T55 128
valid_sources[0x4c] 507 1 T247 4 T71 14 T200 1
valid_sources[0x4d] 378 1 T21 1 T71 17 T72 20
valid_sources[0x4e] 449 1 T71 30 T221 1 T72 22
valid_sources[0x4f] 393 1 T50 1 T34 1 T255 2
valid_sources[0x50] 345 1 T71 21 T72 9 T116 26
valid_sources[0x51] 586 1 T34 182 T25 1 T71 15
valid_sources[0x52] 323 1 T6 1 T124 1 T34 2
valid_sources[0x53] 604 1 T262 4 T175 4 T109 1
valid_sources[0x54] 268 1 T122 1 T34 1 T36 2
valid_sources[0x55] 314 1 T34 2 T239 1 T71 20
valid_sources[0x56] 579 1 T34 20 T256 5 T71 17
valid_sources[0x57] 401 1 T252 1 T71 24 T235 1
valid_sources[0x58] 383 1 T263 2 T264 1 T265 2
valid_sources[0x59] 429 1 T71 11 T72 6 T266 2
valid_sources[0x5a] 348 1 T250 4 T71 22 T72 5
valid_sources[0x5b] 291 1 T71 18 T72 2 T116 20
valid_sources[0x5c] 299 1 T45 2 T22 1 T34 4
valid_sources[0x5d] 461 1 T28 4 T71 12 T72 15
valid_sources[0x5e] 922 1 T21 1 T34 2 T71 18
valid_sources[0x5f] 455 1 T4 1 T71 24 T72 11
valid_sources[0x60] 623 1 T265 2 T71 15 T72 5
valid_sources[0x61] 349 1 T34 1 T71 25 T267 3
valid_sources[0x62] 436 1 T34 38 T255 1 T71 14
valid_sources[0x63] 799 1 T34 34 T71 15 T72 10
valid_sources[0x64] 305 1 T250 3 T71 32 T229 1
valid_sources[0x65] 529 1 T98 1 T122 1 T34 67
valid_sources[0x66] 430 1 T34 2 T80 1 T71 9
valid_sources[0x67] 303 1 T34 2 T268 10 T225 1
valid_sources[0x68] 326 1 T71 29 T72 11 T55 17
valid_sources[0x69] 407 1 T245 1 T237 1 T71 9
valid_sources[0x6a] 545 1 T43 1 T122 1 T237 2
valid_sources[0x6b] 450 1 T79 1 T22 1 T188 1
valid_sources[0x6c] 522 1 T32 1 T34 1 T224 4
valid_sources[0x6d] 518 1 T71 30 T72 8 T116 25
valid_sources[0x6e] 301 1 T28 1 T237 1 T263 1
valid_sources[0x6f] 272 1 T87 2 T34 1 T205 2
valid_sources[0x70] 346 1 T44 1 T269 1 T242 1
valid_sources[0x71] 258 1 T270 1 T34 2 T125 4
valid_sources[0x72] 444 1 T237 1 T71 17 T72 27
valid_sources[0x73] 371 1 T254 1 T261 9 T71 22
valid_sources[0x74] 554 1 T34 4 T71 27 T260 2
valid_sources[0x75] 235 1 T254 1 T71 20 T72 3
valid_sources[0x76] 447 1 T32 1 T71 14 T229 1
valid_sources[0x77] 420 1 T184 1 T71 23 T72 24
valid_sources[0x78] 523 1 T34 2 T71 17 T72 9
valid_sources[0x79] 220 1 T197 5 T71 23 T72 21
valid_sources[0x7a] 267 1 T271 2 T36 1 T71 17
valid_sources[0x7b] 643 1 T145 1 T237 1 T251 1
valid_sources[0x7c] 573 1 T22 2 T71 31 T72 29
valid_sources[0x7d] 661 1 T254 1 T34 1 T71 22
valid_sources[0x7e] 427 1 T71 23 T72 28 T116 22
valid_sources[0x7f] 848 1 T147 1 T71 35 T72 5
valid_sources[0x80] 301 1 T11 1 T272 1 T71 17



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 28272 1 T34 921 T71 1283 T72 716
values[0x0] all_enables biggest_size 39733 1 T2 1 T14 1 T7 1
values[0x1] all_enables biggest_size 39723 1 T1 1 T3 1 T13 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%