SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1154652 | 1 | T1 | 1 | T3 | 3 | T13 | 1 | ||||
auto[1] | 191712 | 1 | T62 | 80 | T63 | 80 | T34 | 6724 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1346175 | 1 | T1 | 1 | T3 | 3 | T13 | 1 | ||||
values[1] | 16 | 1 | T179 | 2 | T182 | 1 | T209 | 1 | ||||
values[2] | 5 | 1 | T211 | 1 | T212 | 1 | T215 | 1 | ||||
values[3] | 94 | 1 | T179 | 4 | T182 | 3 | T183 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1346171 | 1 | T1 | 1 | T3 | 3 | T13 | 1 | ||||
values[1] | 11 | 1 | T179 | 1 | T207 | 1 | T208 | 1 | ||||
values[2] | 6 | 1 | T216 | 1 | T211 | 1 | T212 | 2 | ||||
values[3] | 90 | 1 | T179 | 1 | T182 | 4 | T183 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1346074 | 1 | T1 | 1 | T3 | 3 | T13 | 1 | ||||
auto[TlIntgErrCmd] | 97 | 1 | T179 | 6 | T182 | 3 | T183 | 3 | ||||
auto[TlIntgErrData] | 101 | 1 | T179 | 1 | T182 | 4 | T183 | 13 | ||||
auto[TlIntgErrBoth] | 92 | 1 | T179 | 3 | T182 | 3 | T183 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 304141 | 0 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 303950 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
values[1] | 15 | 1 | T209 | 1 | T207 | 1 | T216 | 1 | ||||
values[2] | 6 | 1 | T207 | 1 | T211 | 1 | T212 | 1 | ||||
values[3] | 96 | 1 | T182 | 6 | T183 | 6 | T209 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 303950 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
values[1] | 31 | 1 | T179 | 2 | T182 | 2 | T183 | 1 | ||||
values[2] | 3 | 1 | T208 | 1 | T213 | 1 | T206 | 1 | ||||
values[3] | 94 | 1 | T179 | 3 | T182 | 4 | T183 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 303851 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
auto[TlIntgErrCmd] | 99 | 1 | T179 | 3 | T182 | 3 | T183 | 7 | ||||
auto[TlIntgErrData] | 99 | 1 | T179 | 4 | T182 | 2 | T183 | 9 | ||||
auto[TlIntgErrBoth] | 92 | 1 | T179 | 3 | T182 | 5 | T183 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |