Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

728713

1

T1

1

T3

3

T13

1

full_word

617651

1

T14

1

T7

2

T15

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1346074	1			T1	1		T3	3		T13	1
auto[TlIntgErrCmd]	97	1			T179	6		T182	3		T183	3
auto[TlIntgErrData]	101	1			T179	1		T182	4		T183	13
auto[TlIntgErrBoth]	92	1			T179	3		T182	3		T183	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

516379

1

T14

1

T15

3

T44

3

auto[1]

829985

1

T1

1

T3

3

T13

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	216608	1			T14	1		T15	2		T44	2
auto[TlIntgErrNone]	partial	auto[1]	511826	1			T1	1		T3	3		T13	1
auto[TlIntgErrNone]	full_word	auto[0]	299628	1			T15	1		T44	1		T6	1
auto[TlIntgErrNone]	full_word	auto[1]	318012	1			T14	1		T7	2		T15	2
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T179	4		T182	2		T183	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T179	2		T182	1		T183	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T206	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T183	1		T207	1		T208	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T179	1		T182	2		T183	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T182	2		T183	9		T209	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T210	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T179	1		T182	2		T183	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T179	2		T182	1		T183	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T211	1		T208	1		T212	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T213	1		T214	1		-	-