Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 98294065 141826 0 0
late_debug_enable_rd_A 98294065 12063 0 0
late_debug_enable_regwen_rd_A 98294065 10172 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 98294065 141826 0 0
T11 774936 0 0 0
T34 263414 4974 0 0
T55 0 4729 0 0
T71 0 7072 0 0
T72 0 5249 0 0
T74 0 6926 0 0
T75 0 14081 0 0
T82 0 7700 0 0
T84 0 10824 0 0
T116 0 7168 0 0
T117 0 129 0 0
T125 200880 0 0 0
T126 365794 0 0 0
T127 142642 0 0 0
T128 5650 0 0 0
T129 59521 0 0 0
T130 282410 0 0 0
T131 262655 0 0 0
T132 135825 0 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 98294065 12063 0 0
T11 774936 0 0 0
T34 263414 936 0 0
T55 0 1752 0 0
T72 0 1461 0 0
T74 0 2511 0 0
T125 200880 0 0 0
T126 365794 0 0 0
T127 142642 0 0 0
T128 5650 0 0 0
T129 59521 0 0 0
T130 282410 0 0 0
T131 262655 0 0 0
T132 135825 0 0 0
T135 0 9 0 0
T138 0 5 0 0
T140 0 14 0 0
T163 0 2 0 0
T179 0 11 0 0
T180 0 821 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 98294065 10172 0 0
T11 774936 0 0 0
T34 263414 762 0 0
T55 0 1427 0 0
T72 0 1104 0 0
T74 0 2483 0 0
T118 0 10 0 0
T125 200880 0 0 0
T126 365794 0 0 0
T127 142642 0 0 0
T128 5650 0 0 0
T129 59521 0 0 0
T130 282410 0 0 0
T131 262655 0 0 0
T132 135825 0 0 0
T135 0 12 0 0
T136 0 7 0 0
T138 0 11 0 0
T140 0 3 0 0
T179 0 24 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%