Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_dm_top.i_dm_sba

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_dm_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : dm_sba
Line No.TotalCoveredPercent
TOTAL7777100.00
CONT_ASSIGN6911100.00
ALWAYS7277100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9711100.00
ALWAYS1015454100.00
ALWAYS19333100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN20911100.00

68 69 1/1 assign sbbusy_o = logic'(state_q != dm::Idle); Tests: T1 T2 T3  70 71 always_comb begin : p_be_mask 72 1/1 be_mask = '0; Tests: T1 T2 T3  73 74 // generate byte enable mask 75 1/1 unique case (sbaccess_i) Tests: T1 T2 T3  76 3'b000: begin 77 1/1 be_mask[be_idx] = '1; Tests: T2 T19 T40  78 end 79 3'b001: begin 80 1/1 be_mask[int'({be_idx[$high(be_idx):1], 1'b0}) +: 2] = '1; Tests: T2 T19 T40  81 end 82 3'b010: begin 83 1/1(1 unreachable) if (BusWidth == 32'd64) be_mask[int'({be_idx[$high(be_idx)], 2'h0}) +: 4] = '1; Tests: T1 T2 T3  84 1/1 else be_mask = '1; Tests: T1 T2 T3  85 end 86 1/1 3'b011: be_mask = '1; Tests: T19 T40 T103  87 default: ; 88 endcase 89 end 90 91 logic [BusWidth-1:0] sbaccess_mask; 92 1/1 assign sbaccess_mask = {BusWidth{1'b1}} << sbaccess_i; Tests: T1 T2 T3  93 94 logic addr_incr_en; 95 logic [BusWidth-1:0] addr_incr; 96 1/1 assign addr_incr = (addr_incr_en) ? (BusWidth'(1'b1) << sbaccess_i) : '0; Tests: T1 T2 T3  97 1/1 assign sbaddress_o = sbaddress_i + addr_incr; Tests: T1 T2 T3  98 99 100 always_comb begin : p_fsm 101 1/1 req = 1'b0; Tests: T1 T2 T3  102 1/1 address = sbaddress_i; Tests: T1 T2 T3  103 1/1 we = 1'b0; Tests: T1 T2 T3  104 1/1 be = '0; Tests: T1 T2 T3  105 1/1 be_idx = sbaddress_i[BeIdxWidth-1:0]; Tests: T1 T2 T3  106 107 1/1 sberror_o = '0; Tests: T1 T2 T3  108 1/1 sberror_valid_o = 1'b0; Tests: T1 T2 T3  109 110 1/1 addr_incr_en = 1'b0; Tests: T1 T2 T3  111 112 1/1 state_d = state_q; Tests: T1 T2 T3  113 114 1/1 unique case (state_q) Tests: T1 T2 T3  115 dm::Idle: begin 116 // debugger requested a read 117 2/2 if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = dm::Read; Tests: T1 T2 T3  | T2 T19 T20  MISSING_ELSE 118 // debugger requested a write 119 2/2 if (sbdata_write_valid_i) state_d = dm::Write; Tests: T1 T2 T3  | T2 T19 T40  MISSING_ELSE 120 // perform another read 121 2/2 if (sbdata_read_valid_i && sbreadondata_i) state_d = dm::Read; Tests: T1 T2 T3  | T2 T19 T40  MISSING_ELSE 122 end 123 124 dm::Read: begin 125 1/1 req = 1'b1; Tests: T2 T19 T20  126 2/2 if (ReadByteEnable) be = be_mask; Tests: T2 T19 T20  | T2 T19 T20  ==> MISSING_ELSE 127 2/2 if (gnt) state_d = dm::WaitRead; Tests: T2 T19 T20  | T2 T19 T20  MISSING_ELSE 128 end 129 130 dm::Write: begin 131 1/1 req = 1'b1; Tests: T2 T19 T40  132 1/1 we = 1'b1; Tests: T2 T19 T40  133 1/1 be = be_mask; Tests: T2 T19 T40  134 2/2 if (gnt) state_d = dm::WaitWrite; Tests: T2 T19 T40  | T2 T19 T40  MISSING_ELSE 135 end 136 137 dm::WaitRead: begin 138 1/1 if (sbdata_valid_o) begin Tests: T2 T19 T20  139 1/1 state_d = dm::Idle; Tests: T2 T19 T20  140 // auto-increment address 141 1/1 addr_incr_en = sbautoincrement_i; Tests: T2 T19 T20  142 // check whether an "other" error has been encountered. 143 1/1 if (master_r_other_err_i) begin Tests: T2 T19 T20  144 1/1 sberror_valid_o = 1'b1; Tests: T19 T43 T122  145 1/1 sberror_o = 3'd7; Tests: T19 T43 T122  146 // check whether there was a bus error (== bad address). 147 1/1 end else if (master_r_err_i) begin Tests: T2 T19 T20  148 1/1 sberror_valid_o = 1'b1; Tests: T40 T43 T88  149 1/1 sberror_o = 3'd2; Tests: T40 T43 T88  150 end MISSING_ELSE 151 end MISSING_ELSE 152 end 153 154 dm::WaitWrite: begin 155 1/1 if (sbdata_valid_o) begin Tests: T2 T19 T40  156 1/1 state_d = dm::Idle; Tests: T2 T19 T40  157 // auto-increment address 158 1/1 addr_incr_en = sbautoincrement_i; Tests: T2 T19 T40  159 // check whether an "other" error has been encountered. 160 1/1 if (master_r_other_err_i) begin Tests: T2 T19 T40  161 1/1 sberror_valid_o = 1'b1; Tests: T19 T43 T122  162 1/1 sberror_o = 3'd7; Tests: T19 T43 T122  163 // check whether there was a bus error (== bad address). 164 1/1 end else if (master_r_err_i) begin Tests: T2 T19 T40  165 1/1 sberror_valid_o = 1'b1; Tests: T19 T40 T103  166 1/1 sberror_o = 3'd2; Tests: T19 T40 T103  167 end MISSING_ELSE 168 end MISSING_ELSE 169 end 170 171 default: state_d = dm::Idle; // catch parasitic state 172 endcase 173 174 // handle error case 175 1/1 if (32'(sbaccess_i) > BeIdxWidth && state_q != dm::Idle) begin Tests: T1 T2 T3  176 1/1 req = 1'b0; Tests: T19 T40 T43  177 1/1 state_d = dm::Idle; Tests: T19 T40 T43  178 1/1 sberror_valid_o = 1'b1; Tests: T19 T40 T43  179 1/1 sberror_o = 3'd4; // unsupported size was requested Tests: T19 T40 T43  180 end MISSING_ELSE 181 182 //if sbaccess_i lsbs of address are not 0 - report misalignment error 183 1/1 if (|(sbaddress_i & ~sbaccess_mask) && state_q != dm::Idle) begin Tests: T1 T2 T3  184 1/1 req = 1'b0; Tests: T19 T40 T43  185 1/1 state_d = dm::Idle; Tests: T19 T40 T43  186 1/1 sberror_valid_o = 1'b1; Tests: T19 T40 T43  187 1/1 sberror_o = 3'd3; // alignment error Tests: T19 T40 T43  188 end MISSING_ELSE 189 // further error handling should go here ... 190 end 191 192 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 193 1/1 if (!rst_ni) begin Tests: T1 T2 T3  194 1/1 state_q <= dm::Idle; Tests: T1 T2 T3  195 end else begin 196 1/1 state_q <= state_d; Tests: T1 T2 T3  197 end 198 end 199 200 logic [BeIdxWidth-1:0] be_idx_masked; 201 1/1 assign be_idx_masked = be_idx & BeIdxWidth'(sbaccess_mask); Tests: T1 T2 T3  202 1/1 assign master_req_o = req; Tests: T1 T2 T3  203 1/1 assign master_add_o = address[BusWidth-1:0]; Tests: T1 T2 T3  204 1/1 assign master_we_o = we; Tests: T1 T2 T3  205 1/1 assign master_wdata_o = sbdata_i[BusWidth-1:0] << (8 * be_idx_masked); Tests: T1 T2 T3  206 1/1 assign master_be_o = be[BusWidth/8-1:0]; Tests: T1 T2 T3  207 1/1 assign gnt = master_gnt_i; Tests: T1 T2 T3  208 1/1 assign sbdata_valid_o = master_r_valid_i; Tests: T1 T2 T3  209 1/1 assign sbdata_o = master_r_rdata_i[BusWidth-1:0] >> (8 * be_idx_masked); Tests: T1 T2 T3 

Cond Coverage for Module : dm_sba
TotalCoveredPercent
Conditions1818100.00
Logical1818100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (addr_incr_en ? ((32'(1'b1) << sbaccess_i)) : '0)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T21,T22

 LINE       117
 EXPRESSION (sbaddress_write_valid_i && sbreadonaddr_i)
             -----------1-----------    -------2------
-1--2-StatusTests
01CoveredT2,T19,T20
10CoveredT2,T19,T40
11CoveredT2,T19,T20

 LINE       121
 EXPRESSION (sbdata_read_valid_i && sbreadondata_i)
             ---------1---------    -------2------
-1--2-StatusTests
01CoveredT2,T19,T40
10CoveredT2,T19,T20
11CoveredT2,T19,T40

 LINE       175
 EXPRESSION ((32'(sbaccess_i) > BeIdxWidth) && (state_q != Idle))
             ---------------1--------------    --------2--------
-1--2-StatusTests
01CoveredT2,T19,T20
10CoveredT19,T40,T43
11CoveredT19,T40,T43

 LINE       175
 SUB-EXPRESSION (state_q != Idle)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T19,T20

 LINE       183
 EXPRESSION (((|(sbaddress_i & (~sbaccess_mask)))) && (state_q != Idle))
             ------------------1------------------    --------2--------
-1--2-StatusTests
01CoveredT2,T19,T20
10CoveredT2,T19,T40
11CoveredT19,T40,T43

 LINE       183
 SUB-EXPRESSION (state_q != Idle)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T19,T20

FSM Coverage for Module : dm_sba
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Idle 139 Covered T1,T2,T3
Read 117 Covered T2,T19,T20
WaitRead 127 Covered T2,T19,T20
WaitWrite 134 Covered T2,T19,T40
Write 119 Covered T2,T19,T40


transitionsLine No.CoveredTests
Idle->Read 117 Covered T2,T19,T20
Idle->Write 119 Covered T2,T19,T40
Read->Idle 177 Covered T19,T40,T43
Read->WaitRead 127 Covered T2,T19,T20
WaitRead->Idle 139 Covered T2,T19,T20
WaitWrite->Idle 156 Covered T2,T19,T40
Write->Idle 177 Covered T19,T40,T43
Write->WaitWrite 134 Covered T2,T19,T40



Branch Coverage for Module : dm_sba
Line No.TotalCoveredPercent
Branches 34 32 94.12
TERNARY 96 2 2 100.00
CASE 75 5 5 100.00
CASE 114 21 19 90.48
IF 175 2 2 100.00
IF 183 2 2 100.00
IF 193 2 2 100.00


96 assign addr_incr = (addr_incr_en) ? (BusWidth'(1'b1) << sbaccess_i) : '0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T19,T21,T22
0 Covered T1,T2,T3


75 unique case (sbaccess_i) -1- 76 3'b000: begin 77 be_mask[be_idx] = '1; ==> 78 end 79 3'b001: begin 80 be_mask[int'({be_idx[$high(be_idx):1], 1'b0}) +: 2] = '1; ==> 81 end 82 3'b010: begin 83 if (BusWidth == 32'd64) be_mask[int'({be_idx[$high(be_idx)], 2'h0}) +: 4] = '1; -2- ==> (Unreachable) 84 else be_mask = '1; ==> 85 end 86 3'b011: be_mask = '1; ==> 87 default: ; ==>

Branches:
-1--2-StatusTests
3'b000 - Covered T2,T19,T40
3'b001 - Covered T2,T19,T40
3'b010 1 Unreachable
3'b010 0 Covered T1,T2,T3
3'b011 - Covered T19,T40,T103
default - Covered T19,T40,T43


114 unique case (state_q) -1- 115 dm::Idle: begin 116 // debugger requested a read 117 if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = dm::Read; -2- ==> MISSING_ELSE ==> 118 // debugger requested a write 119 if (sbdata_write_valid_i) state_d = dm::Write; -3- ==> MISSING_ELSE ==> 120 // perform another read 121 if (sbdata_read_valid_i && sbreadondata_i) state_d = dm::Read; -4- ==> MISSING_ELSE ==> 122 end 123 124 dm::Read: begin 125 req = 1'b1; 126 if (ReadByteEnable) be = be_mask; -5- ==> MISSING_ELSE ==> 127 if (gnt) state_d = dm::WaitRead; -6- ==> MISSING_ELSE ==> 128 end 129 130 dm::Write: begin 131 req = 1'b1; 132 we = 1'b1; 133 be = be_mask; 134 if (gnt) state_d = dm::WaitWrite; -7- ==> MISSING_ELSE ==> 135 end 136 137 dm::WaitRead: begin 138 if (sbdata_valid_o) begin -8- 139 state_d = dm::Idle; 140 // auto-increment address 141 addr_incr_en = sbautoincrement_i; 142 // check whether an "other" error has been encountered. 143 if (master_r_other_err_i) begin -9- 144 sberror_valid_o = 1'b1; ==> 145 sberror_o = 3'd7; 146 // check whether there was a bus error (== bad address). 147 end else if (master_r_err_i) begin -10- 148 sberror_valid_o = 1'b1; ==> 149 sberror_o = 3'd2; 150 end MISSING_ELSE ==> 151 end MISSING_ELSE ==> 152 end 153 154 dm::WaitWrite: begin 155 if (sbdata_valid_o) begin -11- 156 state_d = dm::Idle; 157 // auto-increment address 158 addr_incr_en = sbautoincrement_i; 159 // check whether an "other" error has been encountered. 160 if (master_r_other_err_i) begin -12- 161 sberror_valid_o = 1'b1; ==> 162 sberror_o = 3'd7; 163 // check whether there was a bus error (== bad address). 164 end else if (master_r_err_i) begin -13- 165 sberror_valid_o = 1'b1; ==> 166 sberror_o = 3'd2; 167 end MISSING_ELSE ==> 168 end MISSING_ELSE ==> 169 end 170 171 default: state_d = dm::Idle; // catch parasitic state ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
Idle 1 - - - - - - - - - - - Covered T2,T19,T20
Idle 0 - - - - - - - - - - - Covered T1,T2,T3
Idle - 1 - - - - - - - - - - Covered T2,T19,T40
Idle - 0 - - - - - - - - - - Covered T1,T2,T3
Idle - - 1 - - - - - - - - - Covered T2,T19,T40
Idle - - 0 - - - - - - - - - Covered T1,T2,T3
Read - - - 1 - - - - - - - - Covered T2,T19,T20
Read - - - 0 - - - - - - - - Not Covered
Read - - - - 1 - - - - - - - Covered T2,T19,T20
Read - - - - 0 - - - - - - - Covered T2,T19,T86
Write - - - - - 1 - - - - - - Covered T2,T19,T40
Write - - - - - 0 - - - - - - Covered T2,T19,T86
WaitRead - - - - - - 1 1 - - - - Covered T19,T43,T122
WaitRead - - - - - - 1 0 1 - - - Covered T40,T43,T88
WaitRead - - - - - - 1 0 0 - - - Covered T2,T19,T20
WaitRead - - - - - - 0 - - - - - Covered T2,T19,T20
WaitWrite - - - - - - - - - 1 1 - Covered T19,T43,T122
WaitWrite - - - - - - - - - 1 0 1 Covered T19,T40,T103
WaitWrite - - - - - - - - - 1 0 0 Covered T2,T19,T43
WaitWrite - - - - - - - - - 0 - - Covered T2,T19,T43
default - - - - - - - - - - - - Not Covered


175 if (32'(sbaccess_i) > BeIdxWidth && state_q != dm::Idle) begin -1- 176 req = 1'b0; ==> 177 state_d = dm::Idle; 178 sberror_valid_o = 1'b1; 179 sberror_o = 3'd4; // unsupported size was requested 180 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T19,T40,T43
0 Covered T1,T2,T3


183 if (|(sbaddress_i & ~sbaccess_mask) && state_q != dm::Idle) begin -1- 184 req = 1'b0; ==> 185 state_d = dm::Idle; 186 sberror_valid_o = 1'b1; 187 sberror_o = 3'd3; // alignment error 188 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T19,T40,T43
0 Covered T1,T2,T3


193 if (!rst_ni) begin -1- 194 state_q <= dm::Idle; ==> 195 end else begin 196 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_dm_top.i_dm_sba
Line No.TotalCoveredPercent
TOTAL7777100.00
CONT_ASSIGN6911100.00
ALWAYS7277100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9711100.00
ALWAYS1015454100.00
ALWAYS19333100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20311100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN20811100.00
CONT_ASSIGN20911100.00

68 69 1/1 assign sbbusy_o = logic'(state_q != dm::Idle); Tests: T1 T2 T3  70 71 always_comb begin : p_be_mask 72 1/1 be_mask = '0; Tests: T1 T2 T3  73 74 // generate byte enable mask 75 1/1 unique case (sbaccess_i) Tests: T1 T2 T3  76 3'b000: begin 77 1/1 be_mask[be_idx] = '1; Tests: T2 T19 T40  78 end 79 3'b001: begin 80 1/1 be_mask[int'({be_idx[$high(be_idx):1], 1'b0}) +: 2] = '1; Tests: T2 T19 T40  81 end 82 3'b010: begin 83 1/1(1 unreachable) if (BusWidth == 32'd64) be_mask[int'({be_idx[$high(be_idx)], 2'h0}) +: 4] = '1; Tests: T1 T2 T3  84 1/1 else be_mask = '1; Tests: T1 T2 T3  85 end 86 1/1 3'b011: be_mask = '1; Tests: T19 T40 T103  87 default: ; 88 endcase 89 end 90 91 logic [BusWidth-1:0] sbaccess_mask; 92 1/1 assign sbaccess_mask = {BusWidth{1'b1}} << sbaccess_i; Tests: T1 T2 T3  93 94 logic addr_incr_en; 95 logic [BusWidth-1:0] addr_incr; 96 1/1 assign addr_incr = (addr_incr_en) ? (BusWidth'(1'b1) << sbaccess_i) : '0; Tests: T1 T2 T3  97 1/1 assign sbaddress_o = sbaddress_i + addr_incr; Tests: T1 T2 T3  98 99 100 always_comb begin : p_fsm 101 1/1 req = 1'b0; Tests: T1 T2 T3  102 1/1 address = sbaddress_i; Tests: T1 T2 T3  103 1/1 we = 1'b0; Tests: T1 T2 T3  104 1/1 be = '0; Tests: T1 T2 T3  105 1/1 be_idx = sbaddress_i[BeIdxWidth-1:0]; Tests: T1 T2 T3  106 107 1/1 sberror_o = '0; Tests: T1 T2 T3  108 1/1 sberror_valid_o = 1'b0; Tests: T1 T2 T3  109 110 1/1 addr_incr_en = 1'b0; Tests: T1 T2 T3  111 112 1/1 state_d = state_q; Tests: T1 T2 T3  113 114 1/1 unique case (state_q) Tests: T1 T2 T3  115 dm::Idle: begin 116 // debugger requested a read 117 2/2 if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = dm::Read; Tests: T1 T2 T3  | T2 T19 T20  MISSING_ELSE 118 // debugger requested a write 119 2/2 if (sbdata_write_valid_i) state_d = dm::Write; Tests: T1 T2 T3  | T2 T19 T40  MISSING_ELSE 120 // perform another read 121 2/2 if (sbdata_read_valid_i && sbreadondata_i) state_d = dm::Read; Tests: T1 T2 T3  | T2 T19 T40  MISSING_ELSE 122 end 123 124 dm::Read: begin 125 1/1 req = 1'b1; Tests: T2 T19 T20  126 2/2 if (ReadByteEnable) be = be_mask; Tests: T2 T19 T20  | T2 T19 T20  ==> MISSING_ELSE 127 2/2 if (gnt) state_d = dm::WaitRead; Tests: T2 T19 T20  | T2 T19 T20  MISSING_ELSE 128 end 129 130 dm::Write: begin 131 1/1 req = 1'b1; Tests: T2 T19 T40  132 1/1 we = 1'b1; Tests: T2 T19 T40  133 1/1 be = be_mask; Tests: T2 T19 T40  134 2/2 if (gnt) state_d = dm::WaitWrite; Tests: T2 T19 T40  | T2 T19 T40  MISSING_ELSE 135 end 136 137 dm::WaitRead: begin 138 1/1 if (sbdata_valid_o) begin Tests: T2 T19 T20  139 1/1 state_d = dm::Idle; Tests: T2 T19 T20  140 // auto-increment address 141 1/1 addr_incr_en = sbautoincrement_i; Tests: T2 T19 T20  142 // check whether an "other" error has been encountered. 143 1/1 if (master_r_other_err_i) begin Tests: T2 T19 T20  144 1/1 sberror_valid_o = 1'b1; Tests: T19 T43 T122  145 1/1 sberror_o = 3'd7; Tests: T19 T43 T122  146 // check whether there was a bus error (== bad address). 147 1/1 end else if (master_r_err_i) begin Tests: T2 T19 T20  148 1/1 sberror_valid_o = 1'b1; Tests: T40 T43 T88  149 1/1 sberror_o = 3'd2; Tests: T40 T43 T88  150 end MISSING_ELSE 151 end MISSING_ELSE 152 end 153 154 dm::WaitWrite: begin 155 1/1 if (sbdata_valid_o) begin Tests: T2 T19 T40  156 1/1 state_d = dm::Idle; Tests: T2 T19 T40  157 // auto-increment address 158 1/1 addr_incr_en = sbautoincrement_i; Tests: T2 T19 T40  159 // check whether an "other" error has been encountered. 160 1/1 if (master_r_other_err_i) begin Tests: T2 T19 T40  161 1/1 sberror_valid_o = 1'b1; Tests: T19 T43 T122  162 1/1 sberror_o = 3'd7; Tests: T19 T43 T122  163 // check whether there was a bus error (== bad address). 164 1/1 end else if (master_r_err_i) begin Tests: T2 T19 T40  165 1/1 sberror_valid_o = 1'b1; Tests: T19 T40 T103  166 1/1 sberror_o = 3'd2; Tests: T19 T40 T103  167 end MISSING_ELSE 168 end MISSING_ELSE 169 end 170 171 default: state_d = dm::Idle; // catch parasitic state Exclude Annotation: VC_COV_UNR 172 endcase 173 174 // handle error case 175 1/1 if (32'(sbaccess_i) > BeIdxWidth && state_q != dm::Idle) begin Tests: T1 T2 T3  176 1/1 req = 1'b0; Tests: T19 T40 T43  177 1/1 state_d = dm::Idle; Tests: T19 T40 T43  178 1/1 sberror_valid_o = 1'b1; Tests: T19 T40 T43  179 1/1 sberror_o = 3'd4; // unsupported size was requested Tests: T19 T40 T43  180 end MISSING_ELSE 181 182 //if sbaccess_i lsbs of address are not 0 - report misalignment error 183 1/1 if (|(sbaddress_i & ~sbaccess_mask) && state_q != dm::Idle) begin Tests: T1 T2 T3  184 1/1 req = 1'b0; Tests: T19 T40 T43  185 1/1 state_d = dm::Idle; Tests: T19 T40 T43  186 1/1 sberror_valid_o = 1'b1; Tests: T19 T40 T43  187 1/1 sberror_o = 3'd3; // alignment error Tests: T19 T40 T43  188 end MISSING_ELSE 189 // further error handling should go here ... 190 end 191 192 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 193 1/1 if (!rst_ni) begin Tests: T1 T2 T3  194 1/1 state_q <= dm::Idle; Tests: T1 T2 T3  195 end else begin 196 1/1 state_q <= state_d; Tests: T1 T2 T3  197 end 198 end 199 200 logic [BeIdxWidth-1:0] be_idx_masked; 201 1/1 assign be_idx_masked = be_idx & BeIdxWidth'(sbaccess_mask); Tests: T1 T2 T3  202 1/1 assign master_req_o = req; Tests: T1 T2 T3  203 1/1 assign master_add_o = address[BusWidth-1:0]; Tests: T1 T2 T3  204 1/1 assign master_we_o = we; Tests: T1 T2 T3  205 1/1 assign master_wdata_o = sbdata_i[BusWidth-1:0] << (8 * be_idx_masked); Tests: T1 T2 T3  206 1/1 assign master_be_o = be[BusWidth/8-1:0]; Tests: T1 T2 T3  207 1/1 assign gnt = master_gnt_i; Tests: T1 T2 T3  208 1/1 assign sbdata_valid_o = master_r_valid_i; Tests: T1 T2 T3  209 1/1 assign sbdata_o = master_r_rdata_i[BusWidth-1:0] >> (8 * be_idx_masked); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_dm_top.i_dm_sba
TotalCoveredPercent
Conditions1818100.00
Logical1818100.00
Non-Logical00
Event00

 LINE       96
 EXPRESSION (addr_incr_en ? ((32'(1'b1) << sbaccess_i)) : '0)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT19,T21,T22

 LINE       117
 EXPRESSION (sbaddress_write_valid_i && sbreadonaddr_i)
             -----------1-----------    -------2------
-1--2-StatusTests
01CoveredT2,T19,T20
10CoveredT2,T19,T40
11CoveredT2,T19,T20

 LINE       121
 EXPRESSION (sbdata_read_valid_i && sbreadondata_i)
             ---------1---------    -------2------
-1--2-StatusTests
01CoveredT2,T19,T40
10CoveredT2,T19,T20
11CoveredT2,T19,T40

 LINE       175
 EXPRESSION ((32'(sbaccess_i) > BeIdxWidth) && (state_q != Idle))
             ---------------1--------------    --------2--------
-1--2-StatusTests
01CoveredT2,T19,T20
10CoveredT19,T40,T43
11CoveredT19,T40,T43

 LINE       175
 SUB-EXPRESSION (state_q != Idle)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T19,T20

 LINE       183
 EXPRESSION (((|(sbaddress_i & (~sbaccess_mask)))) && (state_q != Idle))
             ------------------1------------------    --------2--------
-1--2-StatusTests
01CoveredT2,T19,T20
10CoveredT2,T19,T40
11CoveredT19,T40,T43

 LINE       183
 SUB-EXPRESSION (state_q != Idle)
                --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T19,T20

FSM Coverage for Instance : tb.dut.u_dm_top.i_dm_sba
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
Idle 139 Covered T1,T2,T3
Read 117 Covered T2,T19,T20
WaitRead 127 Covered T2,T19,T20
WaitWrite 134 Covered T2,T19,T40
Write 119 Covered T2,T19,T40


transitionsLine No.CoveredTests
Idle->Read 117 Covered T2,T19,T20
Idle->Write 119 Covered T2,T19,T40
Read->Idle 177 Covered T19,T40,T43
Read->WaitRead 127 Covered T2,T19,T20
WaitRead->Idle 139 Covered T2,T19,T20
WaitWrite->Idle 156 Covered T2,T19,T40
Write->Idle 177 Covered T19,T40,T43
Write->WaitWrite 134 Covered T2,T19,T40



Branch Coverage for Instance : tb.dut.u_dm_top.i_dm_sba
Line No.TotalCoveredPercent
Branches 32 32 100.00
TERNARY 96 2 2 100.00
CASE 75 5 5 100.00
CASE 114 19 19 100.00
IF 175 2 2 100.00
IF 183 2 2 100.00
IF 193 2 2 100.00


96 assign addr_incr = (addr_incr_en) ? (BusWidth'(1'b1) << sbaccess_i) : '0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T19,T21,T22
0 Covered T1,T2,T3


75 unique case (sbaccess_i) -1- 76 3'b000: begin 77 be_mask[be_idx] = '1; ==> 78 end 79 3'b001: begin 80 be_mask[int'({be_idx[$high(be_idx):1], 1'b0}) +: 2] = '1; ==> 81 end 82 3'b010: begin 83 if (BusWidth == 32'd64) be_mask[int'({be_idx[$high(be_idx)], 2'h0}) +: 4] = '1; -2- ==> (Unreachable) 84 else be_mask = '1; ==> 85 end 86 3'b011: be_mask = '1; ==> 87 default: ; ==>

Branches:
-1--2-StatusTests
3'b000 - Covered T2,T19,T40
3'b001 - Covered T2,T19,T40
3'b010 1 Unreachable
3'b010 0 Covered T1,T2,T3
3'b011 - Covered T19,T40,T103
default - Covered T19,T40,T43


114 unique case (state_q) -1- 115 dm::Idle: begin 116 // debugger requested a read 117 if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = dm::Read; -2- ==> MISSING_ELSE ==> 118 // debugger requested a write 119 if (sbdata_write_valid_i) state_d = dm::Write; -3- ==> MISSING_ELSE ==> 120 // perform another read 121 if (sbdata_read_valid_i && sbreadondata_i) state_d = dm::Read; -4- ==> MISSING_ELSE ==> 122 end 123 124 dm::Read: begin 125 req = 1'b1; 126 if (ReadByteEnable) be = be_mask; -5- ==> MISSING_ELSE ==> (Excluded) Exclude Annotation: VC_COV_UNR 127 if (gnt) state_d = dm::WaitRead; -6- ==> MISSING_ELSE ==> 128 end 129 130 dm::Write: begin 131 req = 1'b1; 132 we = 1'b1; 133 be = be_mask; 134 if (gnt) state_d = dm::WaitWrite; -7- ==> MISSING_ELSE ==> 135 end 136 137 dm::WaitRead: begin 138 if (sbdata_valid_o) begin -8- 139 state_d = dm::Idle; 140 // auto-increment address 141 addr_incr_en = sbautoincrement_i; 142 // check whether an "other" error has been encountered. 143 if (master_r_other_err_i) begin -9- 144 sberror_valid_o = 1'b1; ==> 145 sberror_o = 3'd7; 146 // check whether there was a bus error (== bad address). 147 end else if (master_r_err_i) begin -10- 148 sberror_valid_o = 1'b1; ==> 149 sberror_o = 3'd2; 150 end MISSING_ELSE ==> 151 end MISSING_ELSE ==> 152 end 153 154 dm::WaitWrite: begin 155 if (sbdata_valid_o) begin -11- 156 state_d = dm::Idle; 157 // auto-increment address 158 addr_incr_en = sbautoincrement_i; 159 // check whether an "other" error has been encountered. 160 if (master_r_other_err_i) begin -12- 161 sberror_valid_o = 1'b1; ==> 162 sberror_o = 3'd7; 163 // check whether there was a bus error (== bad address). 164 end else if (master_r_err_i) begin -13- 165 sberror_valid_o = 1'b1; ==> 166 sberror_o = 3'd2; 167 end MISSING_ELSE ==> 168 end MISSING_ELSE ==> 169 end 170 171 default: state_d = dm::Idle; // catch parasitic state ==> (Excluded) Exclude Annotation: VC_COV_UNR

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTestsExclude Annotation
Idle 1 - - - - - - - - - - - Covered T2,T19,T20
Idle 0 - - - - - - - - - - - Covered T1,T2,T3
Idle - 1 - - - - - - - - - - Covered T2,T19,T40
Idle - 0 - - - - - - - - - - Covered T1,T2,T3
Idle - - 1 - - - - - - - - - Covered T2,T19,T40
Idle - - 0 - - - - - - - - - Covered T1,T2,T3
Read - - - 1 - - - - - - - - Covered T2,T19,T20
Read - - - 0 - - - - - - - - Excluded VC_COV_UNR
Read - - - - 1 - - - - - - - Covered T2,T19,T20
Read - - - - 0 - - - - - - - Covered T2,T19,T86
Write - - - - - 1 - - - - - - Covered T2,T19,T40
Write - - - - - 0 - - - - - - Covered T2,T19,T86
WaitRead - - - - - - 1 1 - - - - Covered T19,T43,T122
WaitRead - - - - - - 1 0 1 - - - Covered T40,T43,T88
WaitRead - - - - - - 1 0 0 - - - Covered T2,T19,T20
WaitRead - - - - - - 0 - - - - - Covered T2,T19,T20
WaitWrite - - - - - - - - - 1 1 - Covered T19,T43,T122
WaitWrite - - - - - - - - - 1 0 1 Covered T19,T40,T103
WaitWrite - - - - - - - - - 1 0 0 Covered T2,T19,T43
WaitWrite - - - - - - - - - 0 - - Covered T2,T19,T43
default - - - - - - - - - - - - Excluded VC_COV_UNR


175 if (32'(sbaccess_i) > BeIdxWidth && state_q != dm::Idle) begin -1- 176 req = 1'b0; ==> 177 state_d = dm::Idle; 178 sberror_valid_o = 1'b1; 179 sberror_o = 3'd4; // unsupported size was requested 180 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T19,T40,T43
0 Covered T1,T2,T3


183 if (|(sbaddress_i & ~sbaccess_mask) && state_q != dm::Idle) begin -1- 184 req = 1'b0; ==> 185 state_d = dm::Idle; 186 sberror_valid_o = 1'b1; 187 sberror_o = 3'd3; // alignment error 188 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T19,T40,T43
0 Covered T1,T2,T3


193 if (!rst_ni) begin -1- 194 state_q <= dm::Idle; ==> 195 end else begin 196 state_q <= state_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

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