Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T98

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98
1	1	Covered	T98

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T98
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	6706293	6704805	0	0
selKnown1	60724029	60722541	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	6706293	6704805	0	0
T1	1698	1696	0	0
T2	13110	13108	0	0
T3	2698	2696	0	0
T4	800	798	0	0
T5	1244	1242	0	0
T7	792	790	0	0
T9	3	1	0	0
T13	1078	1076	0	0
T14	1582	1580	0	0
T15	2688	2686	0	0
T19	8	6	0	0
T27	2	0	0	0
T28	0	4	0	0
T43	0	10	0	0
T44	2932	2930	0	0
T45	11	9	0	0
T46	0	2	0	0
T50	0	1	0	0
T59	2	0	0	0
T62	2	0	0	0
T78	4	2	0	0
T89	4	2	0	0
T91	2	0	0	0
T98	3	1	0	0
T181	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	60724029	60722541	0	0
T1	6597	6595	0	0
T2	19559	19557	0	0
T3	21114	21112	0	0
T4	4676	4674	0	0
T5	27016	27014	0	0
T7	6407	6405	0	0
T9	2	0	0	0
T13	3427	3425	0	0
T14	17353	17351	0	0
T15	3947	3945	0	0
T19	8	6	0	0
T27	2	0	0	0
T28	0	4	0	0
T31	0	8	0	0
T32	0	6	0	0
T43	0	10	0	0
T44	22645	22643	0	0
T45	10	8	0	0
T46	0	2	0	0
T50	0	2	0	0
T51	0	40	0	0
T59	2	0	0	0
T62	2	0	0	0
T78	2	0	0	0
T89	2	0	0	0
T91	2	0	0	0
T92	0	20	0	0
T98	2	0	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T98

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98
1	1	Covered	T98

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T98
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2091670	2091408	0	0
selKnown1	56109515	56109253	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2091670	2091408	0	0
T1	849	848	0	0
T2	6555	6554	0	0
T3	1349	1348	0	0
T4	400	399	0	0
T5	622	621	0	0
T7	396	395	0	0
T13	539	538	0	0
T14	791	790	0	0
T15	1344	1343	0	0
T44	1466	1465	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	56109515	56109253	0	0
T1	5748	5747	0	0
T2	13004	13003	0	0
T3	19765	19764	0	0
T4	4276	4275	0	0
T5	26394	26393	0	0
T7	6011	6010	0	0
T13	2888	2887	0	0
T14	16562	16561	0	0
T15	2603	2602	0	0
T44	21179	21178	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T98

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98
1	1	Covered	T98

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T98
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	791	529	0	0
selKnown1	747	485	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	791	529	0	0
T9	1	0	0	0
T19	4	3	0	0
T27	1	0	0	0
T28	0	2	0	0
T43	0	5	0	0
T45	5	4	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	20	0	0
T59	1	0	0	0
T62	1	0	0	0
T78	2	1	0	0
T89	2	1	0	0
T91	1	0	0	0
T98	1	0	0	0
T181	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	747	485	0	0
T9	1	0	0	0
T19	4	3	0	0
T27	1	0	0	0
T28	0	2	0	0
T31	0	4	0	0
T32	0	3	0	0
T43	0	5	0	0
T45	5	4	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	20	0	0
T59	1	0	0	0
T62	1	0	0	0
T78	1	0	0	0
T89	1	0	0	0
T91	1	0	0	0
T92	0	10	0	0
T98	1	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T98

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98
1	1	Covered	T98

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T98
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4612091	4611609	0	0
selKnown1	4612089	4611607	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4612091	4611609	0	0
T1	849	848	0	0
T2	6555	6554	0	0
T3	1349	1348	0	0
T4	400	399	0	0
T5	622	621	0	0
T7	396	395	0	0
T13	539	538	0	0
T14	791	790	0	0
T15	1344	1343	0	0
T44	1466	1465	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	4612089	4611607	0	0
T1	849	848	0	0
T2	6555	6554	0	0
T3	1349	1348	0	0
T4	400	399	0	0
T5	622	621	0	0
T7	396	395	0	0
T13	539	538	0	0
T14	791	790	0	0
T15	1344	1343	0	0
T44	1466	1465	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T98

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T98
1	1	Covered	T98

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T98
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1741	1259	0	0
selKnown1	1678	1196	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1741	1259	0	0
T9	2	1	0	0
T19	4	3	0	0
T27	1	0	0	0
T28	0	2	0	0
T43	0	5	0	0
T45	6	5	0	0
T46	0	1	0	0
T59	1	0	0	0
T62	1	0	0	0
T78	2	1	0	0
T89	2	1	0	0
T91	1	0	0	0
T98	2	1	0	0
T181	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1678	1196	0	0
T9	1	0	0	0
T19	4	3	0	0
T27	1	0	0	0
T28	0	2	0	0
T31	0	4	0	0
T32	0	3	0	0
T43	0	5	0	0
T45	5	4	0	0
T46	0	1	0	0
T50	0	1	0	0
T51	0	20	0	0
T59	1	0	0	0
T62	1	0	0	0
T78	1	0	0	0
T89	1	0	0	0
T91	1	0	0	0
T92	0	10	0	0
T98	1	0	0	0