SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_reg_regs.u_alert_test | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_reg_regs |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 |
25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3 29 1/1 assign qe = we; Tests: T47 T48 T49 30 unreachable assign qre = re;
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |