Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 5/5 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Module :
prim_lc_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1572 |
1572 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T7 |
6 |
6 |
0 |
0 |
T13 |
6 |
6 |
0 |
0 |
T14 |
6 |
6 |
0 |
0 |
T15 |
6 |
6 |
0 |
0 |
T44 |
6 |
6 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
336552456 |
336192996 |
0 |
0 |
T1 |
34488 |
34146 |
0 |
0 |
T2 |
78024 |
77562 |
0 |
0 |
T3 |
118590 |
118248 |
0 |
0 |
T4 |
25656 |
25068 |
0 |
0 |
T5 |
158364 |
158046 |
0 |
0 |
T7 |
36066 |
35688 |
0 |
0 |
T13 |
17328 |
16776 |
0 |
0 |
T14 |
99372 |
99012 |
0 |
0 |
T15 |
15618 |
15246 |
0 |
0 |
T44 |
127074 |
126750 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
168328545 |
168142092 |
0 |
2358 |
T1 |
17244 |
17064 |
0 |
9 |
T2 |
39012 |
38772 |
0 |
9 |
T3 |
59295 |
59115 |
0 |
9 |
T4 |
12828 |
12525 |
0 |
9 |
T5 |
79182 |
79014 |
0 |
9 |
T7 |
18033 |
17835 |
0 |
9 |
T13 |
8664 |
8379 |
0 |
9 |
T14 |
49686 |
49497 |
0 |
9 |
T15 |
7809 |
7614 |
0 |
9 |
T44 |
63537 |
63366 |
0 |
9 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
168223911 |
168044181 |
0 |
0 |
T1 |
17244 |
17073 |
0 |
0 |
T2 |
39012 |
38781 |
0 |
0 |
T3 |
59295 |
59124 |
0 |
0 |
T4 |
12828 |
12534 |
0 |
0 |
T5 |
79182 |
79023 |
0 |
0 |
T7 |
18033 |
17844 |
0 |
0 |
T13 |
8664 |
8388 |
0 |
0 |
T14 |
49686 |
49506 |
0 |
0 |
T15 |
7809 |
7623 |
0 |
0 |
T44 |
63537 |
63375 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
56109515 |
56049605 |
0 |
0 |
T1 |
5748 |
5691 |
0 |
0 |
T2 |
13004 |
12927 |
0 |
0 |
T3 |
19765 |
19708 |
0 |
0 |
T4 |
4276 |
4178 |
0 |
0 |
T5 |
26394 |
26341 |
0 |
0 |
T7 |
6011 |
5948 |
0 |
0 |
T13 |
2888 |
2796 |
0 |
0 |
T14 |
16562 |
16502 |
0 |
0 |
T15 |
2603 |
2541 |
0 |
0 |
T44 |
21179 |
21125 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
56109515 |
56047364 |
0 |
786 |
T1 |
5748 |
5688 |
0 |
3 |
T2 |
13004 |
12924 |
0 |
3 |
T3 |
19765 |
19705 |
0 |
3 |
T4 |
4276 |
4175 |
0 |
3 |
T5 |
26394 |
26338 |
0 |
3 |
T7 |
6011 |
5945 |
0 |
3 |
T13 |
2888 |
2793 |
0 |
3 |
T14 |
16562 |
16499 |
0 |
3 |
T15 |
2603 |
2538 |
0 |
3 |
T44 |
21179 |
21122 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
56109515 |
56049605 |
0 |
0 |
T1 |
5748 |
5691 |
0 |
0 |
T2 |
13004 |
12927 |
0 |
0 |
T3 |
19765 |
19708 |
0 |
0 |
T4 |
4276 |
4178 |
0 |
0 |
T5 |
26394 |
26341 |
0 |
0 |
T7 |
6011 |
5948 |
0 |
0 |
T13 |
2888 |
2796 |
0 |
0 |
T14 |
16562 |
16502 |
0 |
0 |
T15 |
2603 |
2541 |
0 |
0 |
T44 |
21179 |
21125 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
56109515 |
56047364 |
0 |
786 |
T1 |
5748 |
5688 |
0 |
3 |
T2 |
13004 |
12924 |
0 |
3 |
T3 |
19765 |
19705 |
0 |
3 |
T4 |
4276 |
4175 |
0 |
3 |
T5 |
26394 |
26338 |
0 |
3 |
T7 |
6011 |
5945 |
0 |
3 |
T13 |
2888 |
2793 |
0 |
3 |
T14 |
16562 |
16499 |
0 |
3 |
T15 |
2603 |
2538 |
0 |
3 |
T44 |
21179 |
21122 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_pm_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_pm_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
262 |
262 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
56109515 |
56049605 |
0 |
0 |
T1 |
5748 |
5691 |
0 |
0 |
T2 |
13004 |
12927 |
0 |
0 |
T3 |
19765 |
19708 |
0 |
0 |
T4 |
4276 |
4178 |
0 |
0 |
T5 |
26394 |
26341 |
0 |
0 |
T7 |
6011 |
5948 |
0 |
0 |
T13 |
2888 |
2796 |
0 |
0 |
T14 |
16562 |
16502 |
0 |
0 |
T15 |
2603 |
2541 |
0 |
0 |
T44 |
21179 |
21125 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
56109515 |
56047364 |
0 |
786 |
T1 |
5748 |
5688 |
0 |
3 |
T2 |
13004 |
12924 |
0 |
3 |
T3 |
19765 |
19705 |
0 |
3 |
T4 |
4276 |
4175 |
0 |
3 |
T5 |
26394 |
26338 |
0 |
3 |
T7 |
6011 |
5945 |
0 |
3 |
T13 |
2888 |
2793 |
0 |
3 |
T14 |
16562 |
16499 |
0 |
3 |
T15 |
2603 |
2538 |
0 |
3 |
T44 |
21179 |
21122 |
0 |
3 |