Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	276422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

619659

1

T13

1

T14

2

T15

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	509664	1			T14	1		T15	1		T42	3
values[0x0]	163581	1			T11	1		T13	2		T14	2
values[0x1]	222836	1			T11	2		T12	1		T44	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	183251	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

712830

1

T13

1

T14

2

T15

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3361	1			T54	17		T17	23		T62	24
valid_sources[0x01]	3087	1			T56	3		T59	2		T54	7
valid_sources[0x02]	3405	1			T54	10		T17	24		T108	16
valid_sources[0x03]	3225	1			T31	1		T54	17		T17	23
valid_sources[0x04]	3336	1			T54	11		T190	7		T17	18
valid_sources[0x05]	3408	1			T51	1		T54	16		T17	19
valid_sources[0x06]	3661	1			T49	22		T51	2		T54	5
valid_sources[0x07]	3400	1			T54	4		T17	23		T62	12
valid_sources[0x08]	3359	1			T59	1		T54	14		T17	37
valid_sources[0x09]	3558	1			T54	11		T61	1		T17	22
valid_sources[0x0a]	3875	1			T54	19		T17	26		T108	10
valid_sources[0x0b]	3224	1			T54	8		T17	17		T62	18
valid_sources[0x0c]	3241	1			T54	8		T17	13		T108	6
valid_sources[0x0d]	3312	1			T42	1		T54	11		T17	29
valid_sources[0x0e]	4715	1			T92	2		T54	9		T17	19
valid_sources[0x0f]	2984	1			T54	8		T17	25		T108	16
valid_sources[0x10]	4589	1			T54	18		T17	15		T62	211
valid_sources[0x11]	3786	1			T54	27		T17	36		T108	12
valid_sources[0x12]	3224	1			T47	3		T54	21		T61	1
valid_sources[0x13]	3212	1			T59	1		T54	19		T17	30
valid_sources[0x14]	3768	1			T54	10		T17	24		T108	7
valid_sources[0x15]	3215	1			T59	2		T80	1		T54	18
valid_sources[0x16]	3190	1			T52	1		T54	6		T17	23
valid_sources[0x17]	3431	1			T42	1		T54	11		T17	39
valid_sources[0x18]	3391	1			T54	9		T17	24		T108	19
valid_sources[0x19]	3536	1			T54	29		T17	25		T108	15
valid_sources[0x1a]	3476	1			T54	6		T17	38		T108	9
valid_sources[0x1b]	3635	1			T54	23		T17	28		T108	20
valid_sources[0x1c]	3329	1			T54	5		T17	27		T108	11
valid_sources[0x1d]	3634	1			T54	11		T17	30		T108	18
valid_sources[0x1e]	4225	1			T54	34		T17	26		T108	8
valid_sources[0x1f]	3303	1			T48	2		T52	1		T54	13
valid_sources[0x20]	3449	1			T54	14		T17	27		T62	107
valid_sources[0x21]	3940	1			T54	15		T17	16		T108	17
valid_sources[0x22]	3153	1			T54	17		T17	19		T62	98
valid_sources[0x23]	3211	1			T54	11		T17	15		T108	19
valid_sources[0x24]	4437	1			T54	9		T17	23		T108	11
valid_sources[0x25]	4019	1			T54	17		T17	30		T108	18
valid_sources[0x26]	5614	1			T54	17		T17	22		T108	11
valid_sources[0x27]	3426	1			T54	21		T17	23		T62	73
valid_sources[0x28]	3313	1			T54	9		T17	33		T62	20
valid_sources[0x29]	3455	1			T54	17		T17	28		T108	15
valid_sources[0x2a]	3440	1			T54	9		T61	1		T17	13
valid_sources[0x2b]	3400	1			T55	1		T30	6		T54	15
valid_sources[0x2c]	3854	1			T59	4		T54	17		T17	22
valid_sources[0x2d]	3430	1			T54	8		T17	29		T108	19
valid_sources[0x2e]	3330	1			T43	9		T54	27		T17	38
valid_sources[0x2f]	3650	1			T54	19		T17	36		T62	32
valid_sources[0x30]	3405	1			T55	1		T31	1		T54	6
valid_sources[0x31]	3181	1			T54	11		T17	26		T62	102
valid_sources[0x32]	3130	1			T59	1		T54	13		T17	17
valid_sources[0x33]	3419	1			T54	18		T17	36		T108	15
valid_sources[0x34]	3693	1			T54	10		T17	18		T108	15
valid_sources[0x35]	3103	1			T54	9		T17	23		T108	13
valid_sources[0x36]	2880	1			T54	11		T17	34		T108	8
valid_sources[0x37]	3595	1			T76	2		T54	3		T17	30
valid_sources[0x38]	4077	1			T84	1		T54	5		T17	27
valid_sources[0x39]	3134	1			T59	16		T54	10		T17	29
valid_sources[0x3a]	3275	1			T54	9		T17	34		T108	20
valid_sources[0x3b]	3718	1			T50	1		T54	14		T17	33
valid_sources[0x3c]	3529	1			T54	15		T17	31		T62	47
valid_sources[0x3d]	3662	1			T55	1		T54	14		T8	1
valid_sources[0x3e]	3579	1			T54	7		T17	19		T108	10
valid_sources[0x3f]	3150	1			T42	1		T40	2		T54	14
valid_sources[0x40]	3614	1			T54	15		T17	34		T108	11
valid_sources[0x41]	3311	1			T54	15		T17	27		T108	16
valid_sources[0x42]	3787	1			T54	11		T17	31		T62	4
valid_sources[0x43]	3397	1			T83	1		T54	9		T17	27
valid_sources[0x44]	3272	1			T54	11		T17	37		T108	13
valid_sources[0x45]	3541	1			T84	1		T54	5		T17	23
valid_sources[0x46]	3650	1			T54	17		T17	23		T62	57
valid_sources[0x47]	3297	1			T54	12		T17	25		T62	44
valid_sources[0x48]	3373	1			T54	13		T17	22		T62	4
valid_sources[0x49]	3578	1			T54	21		T17	30		T108	14
valid_sources[0x4a]	3413	1			T54	6		T17	21		T62	56
valid_sources[0x4b]	3330	1			T91	1		T54	7		T17	29
valid_sources[0x4c]	3289	1			T54	12		T17	17		T108	15
valid_sources[0x4d]	3909	1			T54	19		T17	32		T108	14
valid_sources[0x4e]	3287	1			T54	14		T17	34		T108	16
valid_sources[0x4f]	3761	1			T54	12		T17	18		T62	319
valid_sources[0x50]	3747	1			T54	26		T17	28		T108	17
valid_sources[0x51]	2991	1			T59	2		T54	14		T17	27
valid_sources[0x52]	3424	1			T54	11		T17	30		T62	2
valid_sources[0x53]	3568	1			T54	1		T61	1		T17	26
valid_sources[0x54]	3593	1			T54	36		T17	29		T62	28
valid_sources[0x55]	3699	1			T54	10		T17	20		T108	11
valid_sources[0x56]	3844	1			T50	1		T54	21		T17	29
valid_sources[0x57]	3288	1			T54	18		T17	27		T62	50
valid_sources[0x58]	3294	1			T84	1		T54	14		T17	32
valid_sources[0x59]	3182	1			T54	7		T26	3		T17	42
valid_sources[0x5a]	2906	1			T52	1		T54	13		T17	37
valid_sources[0x5b]	3439	1			T54	22		T17	33		T108	15
valid_sources[0x5c]	3097	1			T54	15		T17	14		T108	10
valid_sources[0x5d]	3382	1			T14	1		T54	20		T17	27
valid_sources[0x5e]	3546	1			T54	13		T17	22		T108	18
valid_sources[0x5f]	3199	1			T54	8		T17	25		T108	14
valid_sources[0x60]	3533	1			T54	9		T17	27		T108	9
valid_sources[0x61]	3926	1			T54	5		T8	2		T17	22
valid_sources[0x62]	3054	1			T57	1		T54	17		T17	42
valid_sources[0x63]	3875	1			T54	13		T17	40		T108	10
valid_sources[0x64]	3410	1			T54	21		T17	31		T108	18
valid_sources[0x65]	3496	1			T54	12		T61	1		T17	21
valid_sources[0x66]	3681	1			T54	14		T17	29		T108	16
valid_sources[0x67]	3529	1			T54	20		T17	31		T108	12
valid_sources[0x68]	3308	1			T48	2		T54	6		T17	24
valid_sources[0x69]	3327	1			T55	1		T54	14		T17	27
valid_sources[0x6a]	3221	1			T54	12		T17	18		T108	21
valid_sources[0x6b]	3719	1			T54	11		T17	33		T108	11
valid_sources[0x6c]	3557	1			T59	1		T54	17		T17	20
valid_sources[0x6d]	3360	1			T54	7		T17	27		T108	19
valid_sources[0x6e]	3654	1			T54	6		T17	30		T62	30
valid_sources[0x6f]	3285	1			T54	23		T17	28		T62	1
valid_sources[0x70]	3392	1			T55	1		T54	7		T17	17
valid_sources[0x71]	3228	1			T54	11		T17	29		T108	9
valid_sources[0x72]	3503	1			T59	1		T54	10		T17	15
valid_sources[0x73]	3127	1			T54	8		T61	1		T17	27
valid_sources[0x74]	3124	1			T54	15		T17	31		T62	1
valid_sources[0x75]	4041	1			T54	7		T8	1		T17	27
valid_sources[0x76]	3326	1			T54	6		T17	25		T108	8
valid_sources[0x77]	3240	1			T59	4		T54	13		T17	26
valid_sources[0x78]	3734	1			T54	11		T17	32		T62	14
valid_sources[0x79]	3430	1			T47	2		T54	15		T17	33
valid_sources[0x7a]	3771	1			T54	11		T17	24		T108	20
valid_sources[0x7b]	3248	1			T54	12		T17	36		T62	150
valid_sources[0x7c]	2814	1			T80	1		T54	17		T222	1
valid_sources[0x7d]	3528	1			T54	14		T17	34		T108	17
valid_sources[0x7e]	3361	1			T54	10		T17	22		T108	15
valid_sources[0x7f]	3328	1			T54	16		T17	23		T108	9
valid_sources[0x80]	3603	1			T13	2		T54	24		T17	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

307684

1

T14

1

T42

3

T55

5

values[0x0]

all_enables

biggest_size

155933

1

T13

1

T14

1

T5

2

values[0x1]

all_enables

biggest_size

156042

1

T15

1

T30

2

T31

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115200

1

T1

1

T2

1

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34621	1			T54	457		T17	1001		T62	906
values[0x0]	43393	1			T3	2		T14	1		T45	1
values[0x1]	45826	1			T1	1		T2	1		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

118197

1

T1

1

T2

1

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	614	1			T90	1		T62	7		T108	5
valid_sources[0x01]	533	1			T62	12		T108	5		T34	102
valid_sources[0x02]	489	1			T66	1		T62	11		T108	11
valid_sources[0x03]	544	1			T69	2		T62	8		T108	12
valid_sources[0x04]	712	1			T54	2		T62	15		T108	10
valid_sources[0x05]	452	1			T54	74		T62	20		T108	11
valid_sources[0x06]	300	1			T17	2		T62	16		T108	12
valid_sources[0x07]	546	1			T87	1		T54	28		T62	9
valid_sources[0x08]	680	1			T62	17		T108	5		T34	36
valid_sources[0x09]	384	1			T22	6		T23	1		T54	3
valid_sources[0x0a]	515	1			T17	84		T62	16		T108	10
valid_sources[0x0b]	294	1			T92	1		T17	1		T62	16
valid_sources[0x0c]	431	1			T80	1		T54	5		T62	21
valid_sources[0x0d]	388	1			T130	1		T62	10		T108	8
valid_sources[0x0e]	314	1			T41	1		T62	19		T27	1
valid_sources[0x0f]	311	1			T49	1		T54	1		T62	9
valid_sources[0x10]	539	1			T17	5		T62	13		T108	13
valid_sources[0x11]	465	1			T54	31		T222	1		T62	9
valid_sources[0x12]	797	1			T54	12		T62	12		T108	8
valid_sources[0x13]	382	1			T54	34		T62	12		T108	4
valid_sources[0x14]	635	1			T62	12		T108	8		T34	168
valid_sources[0x15]	393	1			T62	16		T165	1		T108	9
valid_sources[0x16]	252	1			T12	1		T23	1		T78	1
valid_sources[0x17]	704	1			T62	13		T108	7		T34	183
valid_sources[0x18]	305	1			T62	10		T108	6		T34	2
valid_sources[0x19]	359	1			T62	13		T108	9		T132	1
valid_sources[0x1a]	743	1			T65	1		T84	1		T54	32
valid_sources[0x1b]	517	1			T62	16		T108	5		T9	13
valid_sources[0x1c]	772	1			T44	1		T54	15		T62	8
valid_sources[0x1d]	596	1			T55	1		T62	12		T108	11
valid_sources[0x1e]	390	1			T223	1		T54	57		T17	6
valid_sources[0x1f]	479	1			T62	16		T108	13		T34	1
valid_sources[0x20]	781	1			T54	61		T17	142		T62	16
valid_sources[0x21]	311	1			T62	15		T108	9		T9	12
valid_sources[0x22]	507	1			T62	18		T108	7		T34	127
valid_sources[0x23]	565	1			T62	23		T108	8		T224	1
valid_sources[0x24]	354	1			T62	11		T108	9		T9	7
valid_sources[0x25]	557	1			T54	86		T62	8		T108	7
valid_sources[0x26]	627	1			T97	1		T54	29		T62	15
valid_sources[0x27]	753	1			T54	2		T17	7		T62	14
valid_sources[0x28]	563	1			T62	13		T108	17		T34	71
valid_sources[0x29]	520	1			T62	17		T108	6		T34	99
valid_sources[0x2a]	506	1			T84	1		T54	5		T62	18
valid_sources[0x2b]	573	1			T6	1		T62	7		T108	4
valid_sources[0x2c]	319	1			T52	1		T62	16		T108	19
valid_sources[0x2d]	399	1			T62	15		T108	5		T34	5
valid_sources[0x2e]	669	1			T17	4		T62	18		T108	7
valid_sources[0x2f]	362	1			T49	1		T62	12		T108	7
valid_sources[0x30]	361	1			T62	10		T108	2		T9	13
valid_sources[0x31]	290	1			T62	10		T108	2		T34	1
valid_sources[0x32]	383	1			T54	1		T164	3		T62	9
valid_sources[0x33]	498	1			T17	53		T62	17		T108	8
valid_sources[0x34]	469	1			T54	1		T62	10		T27	1
valid_sources[0x35]	542	1			T17	57		T62	11		T108	9
valid_sources[0x36]	488	1			T62	13		T165	1		T108	7
valid_sources[0x37]	461	1			T11	1		T49	1		T54	2
valid_sources[0x38]	505	1			T62	22		T108	4		T195	1
valid_sources[0x39]	437	1			T62	12		T108	5		T9	14
valid_sources[0x3a]	584	1			T15	1		T54	5		T62	12
valid_sources[0x3b]	370	1			T51	1		T62	19		T108	5
valid_sources[0x3c]	789	1			T43	1		T54	54		T62	19
valid_sources[0x3d]	421	1			T70	1		T54	32		T164	1
valid_sources[0x3e]	378	1			T87	1		T54	1		T62	15
valid_sources[0x3f]	312	1			T190	1		T62	14		T108	14
valid_sources[0x40]	367	1			T62	14		T108	8		T34	60
valid_sources[0x41]	335	1			T54	1		T26	1		T62	16
valid_sources[0x42]	546	1			T84	1		T54	19		T62	16
valid_sources[0x43]	460	1			T49	1		T54	18		T62	16
valid_sources[0x44]	516	1			T1	1		T62	14		T108	9
valid_sources[0x45]	464	1			T225	1		T62	12		T108	8
valid_sources[0x46]	550	1			T5	1		T65	1		T54	29
valid_sources[0x47]	632	1			T54	4		T17	1		T62	11
valid_sources[0x48]	424	1			T85	1		T54	1		T17	1
valid_sources[0x49]	554	1			T54	53		T204	1		T62	10
valid_sources[0x4a]	534	1			T87	1		T54	28		T182	1
valid_sources[0x4b]	420	1			T62	16		T108	5		T185	1
valid_sources[0x4c]	339	1			T67	2		T87	1		T54	1
valid_sources[0x4d]	546	1			T226	3		T54	5		T17	76
valid_sources[0x4e]	529	1			T62	11		T108	5		T34	123
valid_sources[0x4f]	438	1			T54	1		T62	17		T108	23
valid_sources[0x50]	473	1			T17	104		T62	10		T108	5
valid_sources[0x51]	284	1			T53	1		T62	12		T108	4
valid_sources[0x52]	352	1			T17	5		T62	8		T108	14
valid_sources[0x53]	684	1			T54	1		T62	14		T108	16
valid_sources[0x54]	433	1			T84	1		T54	1		T17	141
valid_sources[0x55]	691	1			T91	1		T17	125		T62	16
valid_sources[0x56]	632	1			T54	47		T62	14		T108	12
valid_sources[0x57]	688	1			T54	15		T62	12		T108	8
valid_sources[0x58]	535	1			T54	2		T62	12		T108	12
valid_sources[0x59]	295	1			T62	12		T108	11		T227	1
valid_sources[0x5a]	355	1			T54	35		T17	2		T62	8
valid_sources[0x5b]	462	1			T3	1		T77	2		T228	1
valid_sources[0x5c]	662	1			T3	2		T54	26		T62	13
valid_sources[0x5d]	359	1			T54	1		T62	11		T108	7
valid_sources[0x5e]	328	1			T62	21		T108	10		T34	3
valid_sources[0x5f]	751	1			T62	14		T108	5		T34	1
valid_sources[0x60]	353	1			T54	5		T62	11		T108	10
valid_sources[0x61]	508	1			T3	2		T62	17		T108	11
valid_sources[0x62]	455	1			T54	4		T62	16		T108	8
valid_sources[0x63]	497	1			T57	1		T54	3		T62	16
valid_sources[0x64]	337	1			T54	2		T62	9		T108	4
valid_sources[0x65]	297	1			T62	12		T108	6		T34	2
valid_sources[0x66]	553	1			T17	1		T62	9		T108	9
valid_sources[0x67]	333	1			T23	1		T54	33		T62	10
valid_sources[0x68]	430	1			T62	10		T108	7		T9	9
valid_sources[0x69]	542	1			T93	1		T17	210		T62	21
valid_sources[0x6a]	527	1			T62	12		T108	5		T9	18
valid_sources[0x6b]	881	1			T59	1		T8	9		T62	9
valid_sources[0x6c]	346	1			T54	1		T62	12		T108	13
valid_sources[0x6d]	307	1			T62	17		T108	11		T227	1
valid_sources[0x6e]	776	1			T75	1		T85	5		T62	14
valid_sources[0x6f]	980	1			T54	14		T17	219		T62	7
valid_sources[0x70]	510	1			T115	1		T17	3		T62	16
valid_sources[0x71]	588	1			T54	3		T62	20		T108	3
valid_sources[0x72]	364	1			T62	14		T108	8		T9	7
valid_sources[0x73]	281	1			T62	13		T108	7		T34	2
valid_sources[0x74]	345	1			T17	1		T62	14		T108	8
valid_sources[0x75]	413	1			T26	2		T62	10		T108	4
valid_sources[0x76]	321	1			T54	24		T118	6		T62	9
valid_sources[0x77]	412	1			T62	12		T108	13		T34	1
valid_sources[0x78]	891	1			T226	1		T54	124		T17	126
valid_sources[0x79]	331	1			T25	1		T62	12		T108	11
valid_sources[0x7a]	365	1			T87	1		T54	10		T62	13
valid_sources[0x7b]	701	1			T17	48		T62	16		T108	17
valid_sources[0x7c]	311	1			T62	15		T108	13		T34	4
valid_sources[0x7d]	808	1			T23	1		T62	14		T108	5
valid_sources[0x7e]	342	1			T62	19		T108	11		T9	6
valid_sources[0x7f]	384	1			T66	1		T62	11		T108	6
valid_sources[0x80]	595	1			T54	20		T17	181		T62	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30330

1

T54

422

T17

921

T62

844

values[0x0]

all_enables

biggest_size

42405

1

T3

2

T14

1

T45

1

values[0x1]

all_enables

biggest_size

42465

1

T1

1

T2

1

T3

3